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AD9515BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
Data Sheet AD9515
Rev. A | Page 9 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
CMOS OUTPUT ADDITIVE TIME JITTER Delay off
CLK = 400 MHz 290 fs rms Calculated from SNR of ADC method
CMOS (OUT1) = 100 MHz
Divide = 4
CLK = 400 MHz 315 fs rms Calculated from SNR of ADC method
CMOS (OUT1) = 100 MHz
Divide = 4
LVPECL (OUT0) = 50 MHz Interferer
DELAY BLOCK ADDITIVE TIME JITTER
1
100 MHz output; incremental additive jitter
1
Delay FS = 1.5 ns Fine Adj. 00000 0.71 ps rms
Delay FS = 1.5 ns Fine Adj. 11111 1.2 ps rms
Delay FS = 5 ns Fine Adj. 00000 1.3 ps rms
Delay FS = 5 ns Fine Adj. 11111
2.7
ps rms
Delay FS = 10 ns Fine Adj. 00000 2.0 ps rms
Delay FS = 10 ns Fine Adj. 11111 2.8 ps rms
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
SYNCB
Logic High
2.7
V
Logic Low 0.40 V
Capacitance 2 pF
VREF
Output Voltage 0.62 V
S
0.76 V
S
V Minimum − maximum from 0 mA to 1 mA load
S0 TO S10
Levels
0 0.1 V
S
V
1/3 0.2 V
S
0.45 V
S
V
2/3 0.55 V
S
0.8 V
S
V
1 0.9 V
S
V
AD9515 Data Sheet
Rev. A | Page 10 of 28
POWER
Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER-ON SYNCHRONIZATION
1
35 ms See the Power-On SYNC section.
V
S
Transit Time from 2.2 V to 3.1 V
POWER DISSIPATION 215 285 380 mW Both outputs on. LVPECL (divide = 2), LVDS (divide = 2). No clock.
Does not include power dissipated in external resistors.
300 370 465 mW Both outputs on. LVPECL (divide = 2), CMOS (divide = 2);
at 62.5 MHz out (5 pF load).
330 405 510 mW Both outputs on. LVPECL, CMOS (divide = 2);
at 125 MHz out (5 pF load).
POWER DELTA
Divider (Divide = 2 to Divide = 1) 15 30 45 mW For each divider. No clock.
LVPECL Output 65 90 125 mW For each output. No clock.
LVDS Output
20
50
85
mW
No clock.
CMOS Output (Static) 30 40 50 mW No clock.
CMOS Output (@ 62.5 MHz) 80 110 140 mW Single-ended. At 62.5 MHz out with 5 pF load.
CMOS Output (@ 125 MHz) 110 150 190 mW Single-ended. At 125 MHz out with 5 pF load.
Delay Block 30 45 65 mW Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz.
1
This is the rise time of the V
S
supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the V
S
to
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.
Data Sheet AD9515
Rev. A | Page 11 of 28
TIMING DIAGRAMS
CLK
t
CMOS
t
CLK
t
LVDS
t
PECL
05597-002
Figure 2. CLK/CLKB to Clock Output Timing, Divide = 1 Mode
DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
05597-064
Figure 3. LVPECL Timing, Differential
05597-065
DIFFERENTIAL
LVDS
80%
20%
t
RL
t
FL
Figure 4. LVDS Timing, Differential
05597-066
SINGLE-ENDED
CMOS
3pF LOAD
80%
20%
t
RC
t
FC
Figure 5. CMOS Timing, Single-Ended, 3 pF Load
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

AD9515BCPZ

Mfr. #:
Buy AD9515BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Clock Drivers & Distribution 1.6GHz Dividers Delay Adj 2 Outputs
Lifecycle:
New from this manufacturer.
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