AD9515 Data Sheet
Rev. A | Page 22 of 28
DIVIDER PHASE OFFSET
The phase offset of OUT0 and OUT1 can be selected (see Table 12
to Table 15). This allows the relative phase of OUT0 and OUT1
to be set.
After a SYNC operation (see the Synchronization section), the
phase offset word of each divider determines the number of
input clock (CLK) cycles to wait before initiating a clock output
edge. By giving each divider a different phase offset, output-to-
output delays can be set in increments of the fast clock period, t
CLK
.
Figure 29 shows four cases, each with the divider set to divide = 4.
By incrementing the phase offset from 0 to 3, the output is
offset from the initial edge by a multiple of t
CLK
.
0 1541 2 3 5 96 7 8 10 1411 12 13
t
CLK
CLOCK INPUT
CLK
DIVIDER OUTPUT
DIV = 4
PHASE = 0
PHASE = 1
PHASE = 2
PHASE = 3
t
CLK
2 × t
CLK
3 × t
CLK
05597-024
Figure 29. Phase Offset—Divider Set for Divide = 4, Phase Set from 0 to 2
For example:
CLK = 491.52 MHz
t
CLK
= 1/491.52 = 2.0345 ns
For Divide = 4:
Phase Offset 0 = 0 ns
Phase Offset 1 = 2.0345 ns
Phase Offset 2 = 4.069 ns
Phase Offset 3 = 6.104 ns
The outputs can also be described as:
Phase Offset 0 = 0°
Phase Offset 1 = 90°
Phase Offset 2 = 180°
Phase Offset 3 = 270°
Setting the phase offset to Phase = 4 results in the same relative
phase as Phase = 0° or 360°.
The resolution of the phase offset is set by the fast clock period
(t
CLK
) at CLK. The maximum unique phase offset is less than the
divide ratio, up to a phase offset of 15.
Phase offsets can be related to degrees by calculating the phase
step for a particular divide ratio:
Phase Step = 360°/Divide Ratio
Using some of the same examples:
Divide = 4
Phase Step = 360°/4 = 90°
Unique Phase Offsets in Degrees Are Phase = 0°, 90°,
180°, 270°
Divide = 9
Phase Step = 360°/9 = 40°
Unique Phase Offsets in Degrees Are Phase = 0°, 40°, 80°,
120°, 160°, 200°, 240°, 280°, 320°
DELAY BLOCK
OUT1 includes an analog delay element that gives variable time
delays (ΔT) in the clock signal passing through that output.
÷N
∅SELECT
LVDS
CMOS
∆T
MUX
OUTPUT
DRIVER
FINE DELAY ADJUST
(16 STEPS)
FULL SCALE : 1.5ns, 5ns, 10ns
CLOCK INPUT
OUT1 ONLY
05596-025
Figure 30. Analog Delay Block
The amount of delay that can be used is determined by the
output frequency. The amount of delay is limited to less than
one-half cycle of the clock period. For example, for a 10 MHz
clock, the delay can extend to the full 10 ns maximum. However,
for a 100 MHz clock, the maximum delay is less than 5 ns (or
half of the period).
The AD9515 allows for the selection of three full-scale delays,
1.5 ns, 5 ns, and 10 ns, set by delay full scale (see Table 10). Each
of these full-scale delays can be scaled by 16 fine adjustment
values, which are set by the delay word (see Table 14 and Table 15).
The delay block adds some jitter to the output. This means that
the delay function should be used primarily for clocking digital
chips, such as FPGA, ASIC, DUC, and DDC, rather than for
supplying a sample clock for data converters. The jitter is higher
for longer full scales because the delay block uses a ramp and
trip points to create the variable delay. A longer ramp means
more noise has a chance of being introduced.
