TJA1083G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 18 January 2018 10 of 41
NXP Semiconductors
TJA1083G
FlexRay node transceiver
6.2.2 Power-down
The behavior of the TJA1083G during power-down is illustrated in Figure 7.
Fig 6. Power-up behavior (example)
STBN
V
CC
V
IO
V
uvr(VCC)
V
th(rec)POR
V
uvr(VIO)
NormalStandbyPower-off
ERRN
RXD
015aaa005
Fig 7. Power-down behavior (example)
TJA1083G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 18 January 2018 11 of 41
NXP Semiconductors
TJA1083G
FlexRay node transceiver
6.3 Remote wake-up
6.3.1 Bus wake-up via wake-up pattern
A valid remote wake-up event occurs when a wake-up pattern is received. A wake-up
pattern consists of at least two consecutive wake-up symbols. A wake-up symbol
comprises a DATA_0 phase lasting longer than t
det(wake)DATA_0
followed by an idle phase
lasting longer than t
det(wake)idle
, provided both wake-up symbols occur within a time span
of t
det(wake)tot
(see Figure 8). The transceiver also wakes up if DATA_1 phases are
substituted for the idle phases.
See Ref. 1 for more details of the wake-up mechanism.
6.3.2 Bus wake-up via dedicated FlexRay data frame
The TJA1083G wake flag is set when a dedicated data frame emulating a valid wake-up
pattern, as shown in Figure 9
, is received.
The DATA_0 and DATA_1 phases of the emulated wake-up symbol are interrupted by the
Byte Start Sequence (BSS) preceding each byte in the data frame. With a data rate of
10 Mbit/s, the interruption has a maximum duration of 130 ns and does not prevent the
transceiver from recognizing the wake-up pattern in the payload.
For longer interruptions at lower data rates (5 Mbit/s and 2.5 Mbit/s), the wake-up pattern
should be used (see Section 6.3.1
).
The wake flag is not set if an invalid wake-up pattern is received. See Ref. 1
for more
details on invalid wake-up patterns.
Fig 8. Bus wake-up timing
0
V
dif
(mV)
0
-500
> t
det(wake)DATA_0
> t
det(wake)idle
> t
det(wake)idle
> t
det(wake)DATA_0
> t
det(wake)DATA_0
> t
det(wake)DATA_0
> t
det(wake)idle
> t
det(wake)idle
wake-up
+500
015aaa007
0
-500
< t
det(wake)tot
wake-up pattern
wake-up symbol wake-up symbol
TJA1083G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 18 January 2018 12 of 41
NXP Semiconductors
TJA1083G
FlexRay node transceiver
6.4 Bus error detection
The TJA1083G detects the following bus errors during transmission:
Short-circuit BP to BM at the ECU connector or on the bus
Short-circuit BP to GND at the ECU connector or on the bus
Short-circuit BM to GND at the ECU connector or on the bus
Short-circuit BP to V
CC
at the ECU connector or on the bus
Short-circuit BM to V
CC
at the ECU connector or on the bus
The bus error flag is not set when a wake-up pattern or a FlexRay Collision Avoidance
Symbol (CAS) is being transmitted or received.
6.5 Fail silent behavior
Three mechanisms guarantee the ‘fail silent’ behavior of the TJA1083G:
The TXEN clamped flag is set if pin TXEN goes LOW for longer than t
detCL(TXEN)
in
Normal mode; the transmitter is disabled.
The BGE clamped flag is set if pin BGE goes HIGH for longer than t
detCL(BGE)
in
Normal mode; no action is taken.
If a loss-of-ground occurs at the transceiver, resulting in the TJA1083G switching to
Power-off mode, no current flows out of the digital input pins (TXD, TXEN, BGE,
STBN, SCLK, SCSN); see Table 3
for details of the behavior of the bus pins.
6.6 TJA1083G flags
The TJA1083G has 11 status/error flags, described in Table 7.
The duration of each interruption is 130 ns.
The transition time from DATA_0 to DATA_1 and vice versa is about 20 ns.
The TJA1083G wake-up flag is set on receipt of the following frame payload:
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
Fig 9. Minimum bus pattern for bus wake-up via dedicated FlexRay data frame
015aaa139
V
dif
0 V
-2000
wake-up
+2000
870
ns
870
ns
870 ns 870 ns
770
ns
130 ns
130
ns
130
ns
5 µs
5 µs 5 µs 5 µs

TJA1083GTT/0Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized TJA1083GTT/TSSOP14//0/REEL 13 Q1 NDP SSB
Lifecycle:
New from this manufacturer.
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