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TJA1083GTT/0Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
TJA1083G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 18 January 2018 13 of 41
NXP Semiconductors
TJA1083G
FlexRay node transceiver
[1] All flags, except for the PWON flag, are reset after a power-on reset.
[2] If an undervoltage has not been detected on pin V
CC
.
[3] If STBN = LOW.
[4] If BGE = HIGH, the Normal mode flag is set, the TEMP HIGH flag is not set, and the TXEN clamped flag is not set.
[5] Flag can only be set or reset in Normal mode or on leaving Normal mode.
[6] If STBN = HIGH.
[7] If STBN = HIGH in SPI mode
[8] The SPI error flag is set when:
a) more than 16 falling edges occur on pin SCLK while pin SCSN = LOW
b) less than 16 falling edges occur on pin SCLK while pin SCSN = LOW.
6.7 TJA1083G status register
The TJA1083G contains a 16-bit status register, of which bits S0 to S4 reflects the state of
the status flags, bits S5 to S10 reflect the state of the error flags and bit S15 is a parity bit.
All flags can be individually read out on pin SDO via a 16-bit SPI interface when the
transceiver is configured in SPI mode. The status register bits are described in Table 8
.
Table 7. TJA1083G flags and set/reset conditions
Flag name Flag type Flag description Set condition Reset condition
[1]
Consequence of
flag set
bus wake status
flag
indicates if a wake-up
event has occurred
wake-up event on bus
in Standby mode
[2]
transition to Normal
mode
RXD LOW;
ERRN LOW
[3]
Normal
mode
status
flag
indicates if the transceiver
is in Normal mode
entering Normal mode leaving Normal mode -
transmitter
enabled
status
flag
indicates the transmitter
status
transmitter enabled
[4]
transmitter disabled -
BGE
clamped
status
flag
indicates if pin BGE is
clamped
BGE HIGH for longer
than t
detCL(BGE)
[5]
BGE LOW
[5]
-
PWON status
flag
indicates when the digital
section is initialized
V
CC
> V
th(rec)POR
transition to Normal
mode
-
bus error error flag indicates if a bus error has
been detected
bus error detected
[5]
no bus error detected or
positive edge on
TXEN
[5]
ERRN LOW
[6]
TEMP
HIGH
error flag indicates if the max.
junction temperature has
been reached
T
vj
> T
j(dis)(high)
[5]
TXEN = HIGH while
T
vj
< T
j(dis)(high)
[5]
ERRN LOW
[6]
;
transmitter disabled
TXEN
clamped
error flag indicates if pin TXEN is
clamped
TXEN LOW for longer
than t
detCL(TXEN)
[5]
TXEN = HIGH
[5]
ERRN LOW
[6]
;
transmitter disabled
UVV
CC
error flag indicates if there is an
undervoltage at pin V
CC
V
CC
< V
uvd(VCC)
for
longer than t
det(uv)(VCC)
V
CC
> V
uvr(VCC)
for
longer than t
rec(uv)(VCC)
ERRN LOW
[6]
;
entering Standby
mode
UVV
IO
error flag indicates if there is an
undervoltage at pin V
IO
V
IO
< V
uvd(VIO)
for
longer than t
det(uv)(VIO)
V
IO
> V
uvr(VIO)
for longer
than t
rec(uv)(VIO)
ERRN LOW
[6]
;
entering Standby
mode
SPI error error flag indicates if an SPI error
has occurred
SPI error detected
[8]
falling edge on SCSN ERRN LOW
[7]
;
SDO goes to a high
impedance state
TJA1083G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 18 January 2018 14 of 41
NXP Semiconductors
TJA1083G
FlexRay node transceiver
[1] Also cleared during Power-off.
6.8 Error signaling
The TJA1083G provides two modes for error indication:
• Simple error indication mode
• SPI mode (default mode)
SPI mode is active on power-up.
To switch to simple error indication mode, SCSN must be held LOW (connected to GND)
and SCLK held HIGH (connected to V
IO
) for longer than t
det(L)(SCLK)
(provided a V
IO
undervoltage has not occurred). When the TJA1083G is in simple error indication mode, a
rising edge on SCSN initiates a transition to SPI mode (again provided a V
IO
undervoltage
has not occurred); see Figure 10
.
Table 8. TJA1083G status register
Status
bit
Flag name Set condition Reset condition
S0 bus wake bus wake flag set bus wake flag cleared
S1 Normal mode Normal mode flag set Normal mode flag cleared
S2 transmitter enabled transmitter enabled flag set transmitter enabled flag cleared
S3 BGE clamped BGE clamped flag set BGE clamped flag cleared
S4 PWON PWON flag set PWON flag cleared and successful
readout
[1]
S5 bus error bus error flag set bus error flag cleared and
successful readout
[1]
S6 TEMP HIGH TEMP HIGH flag set TEMP HIGH flag cleared and
successful readout
[1]
S7 TXEN clamped TXEN clamped flag set TXEN clamped flag cleared and
successful readout
[1]
S8 UVV
CC
UVV
CC
flag set UVV
CC
flag cleared and successful
readout
[1]
S9 UVV
IO
UVV
IO
flag set UVV
IO
flag cleared and successful
readout
[1]
S10 SPI error SPI error flag set SPI error flag cleared and
successful readout
[1]
S11 reserved always LOW
S12 reserved always HIGH
S13 reserved always LOW
S14 reserved always HIGH
S15 parity bit odd parity of status bits even parity of status bits
TJA1083G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 18 January 2018 15 of 41
NXP Semiconductors
TJA1083G
FlexRay node transceiver
If a V
IO
undervoltage condition is detected, it is not possible to switch between SPI mode
and simple error indication mode.
6.8.1 SPI mode
The error flag information in the status register is latched in SPI mode. This means that
the status bit is reset once the status register has been completely read (provided the
corresponding error flag has been reset). If an error condition is detected in Normal mode,
pin ERRN goes LOW (provided one of the error bits, S5 to S10, is set). Pin ERRN goes
HIGH again once all the error bits have been reset.
6.8.2 Simple error indication mode
If an error condition is detected in Normal mode, pin ERRN goes LOW once the relevant
error flag has been set. Pin ERRN stays stable for at least t
ERRNL(min)
and goes HIGH
again when all error conditions have been cleared and all flags have been reset. Error
flags are not latched. It is not possible to read-out the status bits in this mode.
6.9 SPI interface
The TJA1083G includes a 16-bit SPI interface to enable a host to read the status register
when the transceiver is in SPI mode (see Section 6.8
).
While pin SCSN is HIGH, the SDO output is in a high-impedance state. To begin a status
register readout, the host must force pin SCSN LOW. This action causes the SDO pin to
output a LOW level by default. The data on pin SDO is then shifted out on the rising edge
of the clock signal on pin SCLK.
The status bits shifted out on pin SDO are active HIGH. The status bits are refreshed and
pin SDO returned to a high-impedance state once the status register has been read
successfully (after exactly 16 clock cycles) and SCSN has been forced HIGH again. Clock
signals on SCLK are ignored while SCSN is HIGH. The timing diagram for the SPI readout
is illustrated in Figure 11
.
The SLCK period ranges from 500 ns to 100 s (10 kbit/s to 2 Mbit/s).
Fig 10. Timing diagram for configuration of error indication mode
SCSN
(V)
0
V
IO
t
SCLK
(V)
0
V
IO
t
t
det(L)(SCLK)
SPI mode simple error
indication mode
SPI mode
015aaa015
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

TJA1083GTT/0Z

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Buy TJA1083GTT/0Z
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized TJA1083GTT/TSSOP14//0/REEL 13 Q1 NDP SSB
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