TJA1083G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 18 January 2018 7 of 41
NXP Semiconductors
TJA1083G
FlexRay node transceiver
6.1.1.1 Bus activity and idle detection
In Normal mode, bus activity and bus idle are detected as follows:
Bus activity is detected when the absolute differential voltage on the bus lines is
higher than V
i(dif)det(act)
for t
det(act)(bus)
:
If the differential voltage on the bus lines is lower than V
IL(dif)
after bus activity has
been detected, pin RXD switches LOW.
If the differential voltage on the bus lines is higher than V
IH(dif)
after bus activity has
been detected, pin RXD remains HIGH.
Bus idle is detected when the absolute differential voltage on the bus lines is lower
than V
i(dif)det(act)
for t
det(idle)(bus)
. This results in pin RXD being switched HIGH or
staying HIGH.
6.1.2 Standby mode
Standby mode is a low-power mode featuring very low current consumption. In Standby
mode, the transceiver is unable to transmit or receive data since both the transmitter and
the normal receiver are switched off. The low-power receiver is activated to monitor the
bus for wake-up activity, provided an undervoltage has not been detected on pin V
CC
.
The low-power receiver is deactivated if an undervoltage is detected on pin V
CC
- with the
result that the wake flag is not set if a wake-up pattern or dedicated data frame is
received.
Pins ERRN and RXD indicate the status of the wake flag when V
IO
and V
CC
are within
their operating ranges. See Table 3
for a description of pins ERRN and RXD when an
undervoltage is detected on pin V
IO
or pin V
CC
.
The status register cannot be read via the SPI interface if an undervoltage is detected on
pin V
IO
.
The BGE input has no effect in Standby mode.
6.1.3 Power-off mode
The transmitter and the two receivers (normal and low-power) are deactivated in
Power-off mode. As a result, the wake flag is not set if a wake-up pattern or dedicated
data frame is received. If the voltage at V
CC
rises above V
th(rec)POR
, the transceiver
switches to Standby mode and the digital section is reset. If V
CC
later drops below
V
th(det)POR
, the transceiver reverts to Power-off mode (see Section 6.2).
The status register cannot be read via the SPI interface in Power-off mode.
6.1.4 State transitions
Figure 4 shows the TJA1083G state transition diagram. The timing diagram for the ERRN
indication signal during transitions between Normal and Standby modes, when the error
flag is set and the wake flag is not set, is illustrated in Figure 5
and described in Table 6.
TJA1083G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 18 January 2018 8 of 41
NXP Semiconductors
TJA1083G
FlexRay node transceiver
Fig 4. State transitions diagram
Fig 5. State transitions timing (error flag set)
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TJA1083G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 18 January 2018 9 of 41
NXP Semiconductors
TJA1083G
FlexRay node transceiver
[1] See Table 7 for set and reset conditions of all flags.
6.2 Power-up and power-down behavior
6.2.1 Power-up
The TJA1083G has two supply pins: V
CC
(+5 V) and V
IO
(for the voltage level adaptation).
The ramp up of the different power supplies can vary, depending on the state or value of a
number of signals and parameters. The power-up behavior of the TJA1083G is not
affected by the sequence in which power is supplied to these pins or by the voltage ramp
up.
As an example, Figure 6
shows one possible power supply ramp-up scenario. The digital
section of the TJA1083G is supplied by V
CC
. The voltage on pin V
CC
ramps up before the
voltage on pin V
IO
. As long as the voltage on V
CC
remains below the power-on reset
recovery threshold, V
th(rec)POR
, the internal state machine is inactive and the transceiver is
totally passive, remaining in Power-off mode. As soon as the voltage rises above the
V
th(rec)POR
threshold, the internal state machine starts running, setting the PWON flag and
switching the TJA1083G to Standby mode. This initializes the V
CC
and V
IO
under-voltage
flags to the set state (since both V
CC
and V
IO
are actually in undervoltage state just after
power-on).
Once both V
IO
and V
CC
have reached their operating ranges, the under-voltage flags are
reset. The operating mode is then determined by the level on STBN (the TJA1083G
switches to Normal mode if STBN is HIGH and remains in Standby mode if STBN is
LOW), provided V
IO
and V
CC
are above their respective undervoltage recovery levels
(V
uvr(VIO)
and V
uvr(VCC)
).
Table 6. State transitions
indicates the action that initiates a transaction; 1

and 2

are the consequences of a transaction.
Transition UVV
IO
flag
[1]
UVV
CC
flag
[1]
wake flag
[1]
PWON flag
[1]
STBN VCC level
Normal to Standby cleared cleared cleared cleared LV
CC
> V
uvd(VCC)
set cleared cleared cleared H V
CC
> V
uvd(VCC)
cleared set cleared cleared H V
uvd(VCC)
> V
CC
> V
th(det)POR
Standby to Normal cleared cleared 1 cleared 2 cleared HV
CC
> V
uvd(VCC)
cleared cleared 1 cleared 2 cleared H V
CC
> V
uvd(VCC)
cleared cleared 1 cleared 2 cleared H V
uvd(VCC)
> V
CC
> V
th(det)POR
Standby to Power-off X set X X X V
CC
< V
th(det)POR
Power-off to Standby X set X 1 set X V
CC
> V
th(rec)POR

TJA1083GTT/0Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized TJA1083GTT/TSSOP14//0/REEL 13 Q1 NDP SSB
Lifecycle:
New from this manufacturer.
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