MT45W4MW16PBA-70 IT TR Datasheet MT45W4MW16PBA-70 IT TR, MT45W4MW16PBA-70 WT, MT45W4MW16PBA-70 WT TR | P4-P6

PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f Micron Technology, Inc., reserves the right to change products or specifications without notice.

AsyncCellularRAMLOT.fm - Rev. G 10/05 EN

64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory

List of Tables

Table 1: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 2: Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 3: 64Mb Address Patterns for PAR (CR[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 4: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 5: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 6: Maximum Standby Currents for Applying PAR and TCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 7: Maximum Standby Currents for Applying PAR and TCR Settings – Low-Power (L) . . . . . . . . . . . . . .19

Table 8: Deep Power-Down Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 9: Capacitance Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 10: Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 11: READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 12: WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 13: Load Configuration Register Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 14: Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 15: Power-Up Initialization Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 16: Load Configuration Register Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 17: Deep Power-Down Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 18: READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 19: Page Mode READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 20: WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 21: WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 22: WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f Micron Technology, Inc., reserves the right to change products or specifications without notice.

AsyncCellularRAM_2.fm - Rev. G 10/05 EN

64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory

General Description

Micron

CellularRAM™ products are high-speed, CMOS PSRAM memories developed

for low-power, portable applications. The MT45W4MW16PFA is a 64Mb DRAM core

device organized as 4 Meg x 16 bits. This device includes the industry-standard, asyn-

chronous memory interface found on other low-power SRAM or Pseudo SRAM offerings.

Operating voltages have been reduced in an effort to minimize power consumption. The

core voltage has been reduced to a 1.80V operating level. To maintain compatibility with

different memory bus interfaces, CellularRAM devices are available with I/O voltages of

3.0V, 2.5V, or 1.8V.

A user-accessible configuration register (CR) defines how the CellularRAM device per-

forms on-chip refresh and whether page mode read accesses are permitted. This register

is automatically loaded with a default setting during power-up and can be updated at

any time during normal operation.

To operate seamlessly on an asynchronous memory bus, CellularRAM products incor-

porate a transparent self refresh mechanism. The hidden refresh requires no additional

support from the system memory controller and has no significant impact on device

read/write performance.

Special attention has been focused on current consumption during self refresh. Cellular-

RAM products include three system-accessible mechanisms used to minimize refresh

current. Temperature-compensated refresh (TCR) is used to adjust the refresh rate

according to the case temperature. The refresh rate can be decreased at lower tempera-

tures to minimize current consumption during standby. Setting sleep enable (ZZ#) to

LOW enables one of two low-power modes: partial-array refresh (PAR) or deep power-

down (DPD). PAR limits refresh to only that part of the DRAM array that contains essen-

tial data. DPD halts refresh operation altogether and is used when no vital information is

stored in the device. These three refresh mechanisms are accessed through the CR.

Figure 2: Functional Block Diagram: 4 Meg x 16

Note: Functional block diagrams illustrate simplified device operation. See truth table, ball

descriptions, and timing diagrams for detailed information.

A[21:0]

Input/

Output

MUX

and

Buffers

Control

Logic

4,096K x 16

DRAM

Memory

Array

DQ[7:0]

DQ[15:8]

Address Decode

Logic

LB#

UB#

CE#

OE#

ZZ#

Configuration

PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f Micron Technology, Inc., reserves the right to change products or specifications without notice.

AsyncCellularRAM_2.fm - Rev. G 10/05 EN

64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory

General Description

Notes: 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in

select mode, only DQ[7:0] are affected. When UB# only is in the select mode, DQ[15:8] are

affected.

2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data

inputs/outputs are internally isolated from any external influence.

3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.

4. The device will consume active power in this mode whenever addresses are changed.

5. V

IN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve minimum

standby current.

6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.

Table 1: VFBGA Ball Descriptions

VFBGA Ball

Assignment Symbol Type Description

E3, H6, G2, H1,

D3, E4, F4, F3,

G4, G3, H5, H4,

H3, H2, D4, C4,

C3, B4, B3, A5,

A4, A3

A[21:0] Input

Address Inputs: Inputs for the address accessed during READ or WRITE operations.

The address lines are also used to define the value to be loaded into the CR.

A6 ZZ# Input

Sleep Enable: When ZZ# is LOW, the CR can be loaded or the device can enter one

of two low-power modes (DPD or PAR).

B5 CE# Input

Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is

disabled and goes into standby power mode.

A2 OE# Input

Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the

output buffers are disabled.

G5 WE# Input

Write Enable: Enables WRITE operations when LOW.

A1 LB# Input

Lower Byte Enable. DQ[7:0]

B2 UB# Input

Upper Byte Enable. DQ[15:8]

G1, F1, F2, E2,

D2, C2, C1, B1,

G6, F6, F5, E5,

D5, C6, C5, B6

DQ[15:0] Input/

Output

Data Inputs/Outputs.

D6 V

CC Supply

Device Power Supply: (1.70V–1.95V) Power supply for device core operation.

E1 V

CCQ Supply

I/O Power Supply: (1.70V–3.30V) Power supply for input/output buffers.

E6 V

SS Supply

VSS must be connected to ground.

D1 V

SSQ Supply

VSSQ must be connected to ground.

Table 2: Bus Operations

Mode Power CE# WE# OE# LB#/UB# ZZ# DQ[15:0]

Notes

Standby

Standby H X X X H High-Z 2, 5

Read

Active L H L L H Data-Out 1, 4

Write

Active L L X L H Data-In 1, 3, 4

No Operation

Idle L X X X H X 4, 5

PAR

Partial-Array Refresh H X X X L High-Z 6

DPD

Deep Power-Down H X X X L High-Z 6

Load

Configuration

Active L L X X L High-Z

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

MT45W4MW16PBA-70 IT TR

Mfr. #:

Buy MT45W4MW16PBA-70 IT TR

Manufacturer:

Micron

Description:

IC PSRAM 64M PARALLEL 48VFBGA

Lifecycle:

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MT45W4MW16PBA-70 IT TR

MT45W4MW16PBA-70 IT TR

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