PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f Micron Technology, Inc., reserves the right to change products or specifications without notice.
AsyncCellularRAM_2.fm - Rev. G 10/05 EN
8 ©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory
Functional Description
Functional Description
In general, the MT45W4MW16PFA device is a high-density alternative to SRAM and
Pseudo SRAM products, popular in low-power, portable applications. The
MT45W4MW16PFA contains a 67,108,864-bit DRAM core organized as 4,194,304
addresses by 16 bits. This device implements the industry-standard, asynchronous
memory interface found on other low-power SRAM or Pseudo SRAM offerings. Page
mode accesses are also included as a bandwidth-enhancing extension to the asynchro-
nous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor that is used to launch the
power-up initialization process. Initialization will load the CR with its default settings.
V
CC and VCCQ must be applied simultaneously, and when they reach a stable level above
1.70V, the device will require 150µs to complete its self-initialization process (see
Figure 4). During the initialization period, CE# should remain HIGH. When initialization
is complete, the device is ready for normal operation. At power-up, the CR is set to
0070h.
Figure 4: Power-Up Initialization Timing
Bus Operating Modes
The MT45W4MW16PFA CellularRAM product incorporates the industry-standard, asyn-
chronous interface found on other low-power SRAM or Pseudo SRAM offerings. This bus
interface supports asynchronous READ and WRITE operations as well as the band-
width-enhancing page mode READ operation. The specific interface that is supported is
defined by the value loaded into the CR.
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control interface (CE#, OE#, WE#, LB#/UB#). READ opera-
tions (Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping
WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has
elapsed. WRITE operations (Figure 6) occur when CE#, WE#, and LB#/UB# are driven
LOW. During WRITE operations, the level of OE# is a “Don't Care”; WE# will override
OE#. The data to be written will be latched on the rising edge of CE#, WE#, or LB#/UB#
(whichever occurs first). WE# LOW time must be limited to
t
CEM.
Vcc
VccQ
Device Initialization
Vcc = 1.7V
Device ready for
normal operation
t
PU
>
150µs
