DS638F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 13
EP9315
Enhanced Universal Platform SOC Processor
DC Characteristics
Note: 5. For open drain pins, high level output voltage is dependent on the external load.
6. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table S on
page 60). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not
driven and programmed as an input, it should be tied to power or ground through its own resistor.
(T
A
= 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V;
All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)
Parameter Symbol Min Max Unit
High level output voltage Iout = -4 mA (Note 5)
V
oh
0.85 × RVDD - V
Low level output voltage Iout = 4 mA
V
ol
- 0.15 × RVDD V
High level input voltage (Note 6)
V
ih
0.65 × RVDD VDD + 0.3 V
Low level input voltage (Note 6)
V
il
-0.3 0.35 × RVDD V
High level leakage current Vin = 3.3 V (Note 6)
I
ih
-10 µA
Low level leakage current Vin = 0 (Note 6)
I
il
--10 µA
Parameter Min Typ Max Unit
Power Supply Pins (Outputs Unloaded), 25
° C
Power Supply Current: CVDD / VDD_PLL Total
RVDD
-
-
190
45
240
80
mA
mA
Low-Power Mode Supply Current CVDD / VDD_PLL Total
RVDD
-
-
2
1
3.5
2
mA
mA