50 Copyright 2010 Cirrus Logic (All Rights Reserved) DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Inter-IC Sound - I
2
S
Note: t
i2s_clk
is programmable by the user.
Parameter Symbol Min Typ Max Unit
SCLK cycle time
t
clk_per
-
t
i2s_clk
-ns
SCLK high time
t
clk_high
-
(t
i2s_clk
) / 2
-ns
SCLK low time
t
clk_low
-
(t
i2s_clk
) / 2
-ns
SCLK rise/fall time
t
clkrf
148ns
SCLK to LRCLK assert delay time
t
LRd
--3ns
Hold between SCLK assert then LRCLK deassert
or
Hold between LRCLK deassert then SCLK assert
t
LRh
0--ns
SDI to SCLK deassert setup time
t
SDIs
12 - - ns
SDI from SCLK deassert hold time
t
SDIh
0--ns
SCLK assert to SDO delay time
t
SDOd
--9ns
SDO from SCLK assert hold time
t
SDOh
1--ns
Figure 35. Inter-IC Sound (I
2
S) Timing Measurement
SCLK
LRCLK
SDI
t
LRd
t
LRh
t
SDIh
t
clk_high
t
SDIs
t
clk_low
t
clk_per
t
clkrf
t
SDOh
SDO
t
SDOd
