DS638F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 43
EP9315
Enhanced Universal Platform SOC Processor
Note: The definitions for the DIOWn:STOP, IORDY:DDMARDYn:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no
longer in effect after DMARQ and DMACKn are negated.
Figure 29. Host Terminating an Ultra DMA data-out Burst
DMARQ
(device)
DMACKn
(host)
STOP
(host)
DDMARDYn
(device)
HSTROBE
(host)
DD (15:0)
(host)
IDEDA[2:0]
IDECS0n,
IDECS1n
t
DVH
t
DVS
t
LI
t
LI
t
LI
t
MLI
t
SS
t
ACK
t
ACK
t
ACK
t
IORDYZ
CRC
44 Copyright 2010 Cirrus Logic (All Rights Reserved) DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Note: The definitions for the DIOWn:STOP, IORDY:DDMARDYn:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no
longer in effect after DMARQ and DMACKn are negated.
Figure 30. Device Terminating an Ultra DMA data-out Burst
DMARQ
(device)
DMACKn
(host)
STOP
(host)
DDMARDYn
(device)
HSTROBE
(host)
DD (15:0)
(host)
IDEDA[2:0]
IDECS0n,
IDECS1n
t
LI
t
LI
t
RP
t
RFS
t
MLI
t
ACK
t
ACK
t
ACK
t
DVH
t
DVS
t
MLI
t
IORDYZ
CRC
DS638F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 45
EP9315
Enhanced Universal Platform SOC Processor
Ethernet MAC Interface
STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer
(PHY) interface to the wireless medium.
PHY - Ethernet physical layer interface.
Parameter Symbol
Min Typ Max
Unit
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
TXCLK cycle time
t
TX_per
--40040--ns
TXCLK high time
t
TX_high
140 14 200 20 260 26 ns
TXCLK low time
t
TX_low
140 14 200 20 260 26 ns
TXCLK to signal transition delay time
t
TXd
0 0 10 10 25 25 ns
TXCLK rise/fall time
t
TXrf
----55ns
RXCLK cycle time
t
RX_per
--40040--ns
RXCLK high time
t
RX_high
140 14 200 20 260 26 ns
RXCLK low time
t
RX_low
140 14 200 20 260 26 ns
RXDVAL / RXERR setup time
t
RXs
1010----ns
RXDVAL / RXERR hold time
t
RXh
1010----ns
RXCLK rise/fall time
t
RXrf
----55ns
MDC cycle time
t
MDC_per
--400400--ns
MDC high time
t
MDC_high
160160----ns
MDC low time
t
MDC_low
160160----ns
MDC rise/fall time
t
MDCrf
----55ns
MDIO setup time (STA sourced)
t
MDIOs
1010----ns
MDIO hold time (STA sourced)
t
MDIOh
1010----ns
MDC to MDIO signal transition delay time
(PHY sourced)
t
MDIOd
----300300ns

EP9315-IBZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Universal Platfrm ARM9 SOC Prcessor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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