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EP9315-IBZ
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
P49-P51
P52-P54
P55-P57
P58-P60
P61-P63
P64-P64
DS638F2
Copyright 201
0 Cirrus Logic (A
ll Rights Reser
ved)
43
EP9315
Enhanced Univ
ersal Platform SOC Processor
Note:
The definitions for the DIOWn:STOP
, IORDY:DDMARDY
n:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are
no
longer in effect after DMARQ and DMACKn are negated.
Figure 29. Host Terminating
an Ultra DMA data-out Bu
rst
DMARQ
(device)
DMACKn
(host)
STOP
(host)
DDMARDYn
(device)
HSTROBE
(hos
t)
DD (15:0)
(host)
IDEDA[2:0]
IDECS0n,
IDECS1n
t
DVH
t
DVS
t
LI
t
LI
t
LI
t
MLI
t
SS
t
ACK
t
ACK
t
ACK
t
IORDYZ
CRC
44
Copyright 20
10 Cirrus Logi
c (All Rights Rese
rved)
DS638F2
EP9315
Enhanced Universal Platform
SOC Processor
Note:
The definitions for the DIOWn:STOP
, IORDY:DDMARDY
n:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no
longer in effect after DMARQ and DMACKn are negated.
Figure 30. Device Terminatin
g an Ultra DMA data-out
Burst
DMARQ
(device)
DMACKn
(host)
STOP
(host)
DDMARDY
n
(device)
HSTROBE
(host)
DD (15:0)
(host)
IDEDA[2:0]
IDEC
S0n,
IDECS1n
t
LI
t
LI
t
RP
t
RFS
t
MLI
t
ACK
t
ACK
t
ACK
t
DVH
t
DVS
t
MLI
t
IORDYZ
CRC
DS638F2
Copyright 201
0 Cirrus Logic (A
ll Rights Reser
ved)
45
EP9315
Enhanced Univ
ersal Platform SOC Processor
Ethernet MAC Interface
ST
A
- S
tation - Any device that cont
ains an IEEE 802.1
1
conforming Medium Access Control (MAC) and physical layer
(PHY) interfac
e to the wireless medium
.
PHY - Ethernet physical layer interface.
Parameter
Symbol
Min
T
yp
Max
Unit
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
TXCLK cycle time
t
TX_per
--
4
0
0
4
0
--
n
s
TXCLK high time
t
TX_high
140
14
200
20
260
26
ns
TXCLK lo
w time
t
TX_low
140
14
200
20
260
26
ns
TXCLK to signal transition delay time
t
TXd
0
0
10
10
25
25
ns
TXCLK rise/fall time
t
TXrf
----
5
5
n
s
RXCLK cycle time
t
RX_per
--
4
0
0
4
0
--
n
s
RXCLK high time
t
RX_high
140
14
200
20
260
26
ns
RXCLK low time
t
RX_low
140
14
200
20
260
26
ns
RXDV
AL / RXERR setup time
t
RXs
1
0
1
0
----
n
s
RXDV
AL / RXERR hold time
t
RXh
1
0
1
0
----
n
s
RXCLK rise/fall time
t
RXrf
----
5
5
n
s
MDC cycle time
t
MDC_per
--
4
0
0
4
0
0
--
n
s
MDC high time
t
MDC_high
1
6
0
1
6
0
----
n
s
MDC lo
w time
t
MDC_low
1
6
0
1
6
0
----
n
s
MDC rise/fall time
t
MDCrf
----
5
5
n
s
MDIO setup time (ST
A sourced)
t
MDIOs
1
0
1
0
----
n
s
MDIO hold time (ST
A sourced)
t
MDIOh
1
0
1
0
----
n
s
MDC to MDIO signal transition delay time
(PHY sourced)
t
MDIOd
----
3
0
0
3
0
0
n
s
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
P49-P51
P52-P54
P55-P57
P58-P60
P61-P63
P64-P64
EP9315-IBZ
Mfr. #:
Buy EP9315-IBZ
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Universal Platfrm ARM9 SOC Prcessor
Lifecycle:
New from this manufacturer.
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