40 Copyright 2010 Cirrus Logic (All Rights Reserved) DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Note: The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are no
longer in effect after DMARQ and DMACKn are negated.
Figure 25. Host Terminating an Ultra DMA data-in Burst
DMARQ
(device)
DMACKn
(host)
STOP
(host)
HDMARDYn
(host)
DSTROBE
(device)
DD (15:0)
IDEDA[2:0]
IDECS0n,
IDECS1n
t
LI
t
LI
t
RP
t
RFS
t
MLI
t
ACK
t
ACK
t
ACK
t
DVH
t
DVS
t
MLI
t
ZAH
t
AZ
t
IORDYZ
CRC
DS638F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 41
EP9315
Enhanced Universal Platform SOC Processor
Note: The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are not
in effect until DMARQ and DMACKn are asserted.
Figure 26. Initiating an Ultra DMA data-out Burst
DMARQ
(device)
DMACKn
(host)
STOP
(host)
DDMARDYn
(device)
HSTROBE
(host)
DD (15:0)
IDEDA[2:0]
IDECS0n,
IDECS1n
t
UI
t
ACK
t
ACK
t
ACK
t
ENV
t
LI
t
UI
t
DVS
t
DVH
t
ZIORDY
42 Copyright 2010 Cirrus Logic (All Rights Reserved) DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as
cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are
driven by the host.
Figure 27. Sustained Ultra DMA data-out Burst
Note: 1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t
RP
after DDMARDYn is
negated.
2. If the t
SR
timing is not satisfied, the device may receive zero, one, or two more data words from the host.
Figure 28. Device Pausing an Ultra DMA data-out Burst
HSTROBE
(host)
DD (15:0)
(host)
HSTROBE
(device)
DD (15:0)
(device)
t
CYCWR
t
2CYCWR
t
2CYCWR
t
CYCWR
t
DVH
t
DVS
t
DVH
t
DVS
t
DVH
t
DH
t
DS
t
DS
t
DH
t
DH
DD (15:0)
(host)
HSTROBE
(host)
DDMARDYn
(device)
STOP
(host)
DMACKn
(host)
DMARQ
(device)
t
RP
t
SR
t
RFS

EP9315-IBZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Universal Platfrm ARM9 SOC Prcessor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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