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EP9315-IBZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
4 Copyright 2010 Cirrus Logic (All Rights Reserved) DS638F2
EP9315
Enhanced Universal Platform SOC Processor
List of Figures
Figure 1. Timing Diagram Drawing Key .................................................................................14
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement .....................................15
Figure 3. SDRAM Burst Read Cycle Timing Measurement ...................................................16
Figure 4. SDRAM Burst Write Cycle Timing Measurement ...................................................17
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................18
Figure 6. Static Memory Single Word Read Cycle Timing Measurement ..............................19
Figure 7. Static Memory Single Word Write Cycle Timing Measurement ..............................20
Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement ....................21
Figure 9. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement ....................22
Figure 10. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement ................23
Figure 11. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement ................24
Figure 12. Static Memory Burst Read Cycle Timing Measurement .......................................25
Figure 13. Static Memory Burst Write Cycle Timing Measurement .......................................26
Figure 14. Static Memory Single Read Wait Cycle Timing Measurement .............................27
Figure 15. Static Memory Single Write Wait Cycle Timing Measurement ..............................28
Figure 16. Static Memory Turnaround Cycle Timing Measurement .......................................29
Figure 17. PCMCIA Read Cycle Timing Measurement ..........................................................30
Figure 18. PCMCIA Write Cycle Timing Measurement ..........................................................31
Figure 19. Register Transfer to/from Device ..........................................................................33
Figure 20. PIO Data Transfer to/from Device .........................................................................35
Figure 21. Initiating an Ultra DMA data-in Burst .....................................................................37
Figure 22. Sustained Ultra DMA data-in Burst .......................................................................38
Figure 23. Host Pausing an Ultra DMA data-in Burst .............................................................38
Figure 24. Device Terminating an Ultra DMA data-in Burst ...................................................39
Figure 25. Host Terminating an Ultra DMA data-in Burst .......................................................40
Figure 26. Initiating an Ultra DMA data-out Burst ..................................................................41
Figure 27. Sustained Ultra DMA data-out Burst .....................................................................42
Figure 28. Device Pausing an Ultra DMA data-out Burst .......................................................42
Figure 29. Host Terminating an Ultra DMA data-out Burst ....................................................43
Figure 30. Device Terminating an Ultra DMA data-out Burst .................................................44
Figure 31. Ethernet MAC Timing Measurement .....................................................................46
Figure 32. TI Single Transfer Timing Measurement ...............................................................48
Figure 33. Microwire Frame Format, Single Transfer ............................................................48
Figure 34. SPI Format with SPH=1 Timing Measurement .....................................................49
Figure 35. Inter-IC Sound (I2S) Timing Measurement ...........................................................50
Figure 36. AC ‘97 Configuration Timing Measurement ..........................................................51
Figure 37. LCD Timing Measurement ....................................................................................52
Figure 38. ADC Transfer Function .........................................................................................53
Figure 39. JTAG Timing Measurement ..................................................................................54
Figure 40. 352 Pin PBGA Pin Diagram ..................................................................................55
Figure 40. 352 PIN BGA PINOUT .........................................................................................57
DS638F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 5
EP9315
Enhanced Universal Platform SOC Processor
List of Tables
Table A. Change History .......................................................................................................... 2
Table B. General Purpose Memory Interface Pin Assignments .............................................. 6
Table C. IDE Interface Pin Assignments .................................................................................. 7
Table D. Ethernet Media Access Controller Pin Assignments ................................................. 7
Table E. Audio Interfaces Pin Assignment .............................................................................. 7
Table F. LCD Interface Pin Assignments ................................................................................ 8
Table G.Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8
Table H. 64-Key Keypad Interface Pin Assignments ............................................................... 8
Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 9
Table J. Triple Port USB Host Pin Assignments ..................................................................... 9
Table K. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9
Table L. Real-Time Clock with Pin Assignments ................................................................... 10
Table M.PLL and Clocking Pin Assignments ........................................................................ 10
Table N. Interrupt Controller Pin Assignment ........................................................................ 10
Table O.Dual LED Pin Assignments ..................................................................................... 10
Table P. General Purpose Input/Output Pin Assignment ...................................................... 11
Table Q.Reset and Power Management Pin Assignments ................................................... 11
Table R. Hardware Debug Interface ...................................................................................... 11
Table S. PCMCIA Interface ................................................................................................... 11
Table R. 352 Pin Diagram Dimensions .................................................................................. 56
Table S. Pin Descriptions ..................................................................................................... 60
Table T. Pin Multiplex Usage Information ............................................................................. 62
6 Copyright 2010 Cirrus Logic (All Rights Reserved) DS638F2
EP9315
Enhanced Universal Platform SOC Processor
Processor Core - ARM920T
The ARM920T is a Harvard architecture processor with
separate 16-kbyte instruction and data caches with an 8-
word line length but a unified memory. The processor
utilizes a five-stage pipeline consisting of fetch, decode,
execute, memory, and write stages. Key features include:
• ARM (32-bit) and Thumb (16-bit compressed)
Instruction Sets
• 32-bit Advanced Micro-Controller Bus Architecture
(AMBA)
• 16-kbyte Instruction Cache with Lockdown
• 16-kbyte Data Cache (programmable write-through or
write-back) with Lockdown
• MMU for Linux
®
, Microsoft
®
Windows
®
CE and Other
Operating Systems
• Translation Look Aside Buffers with 64 Data and 64
Instruction Entries
• Programmable Page Sizes of 1 Mbyte, 64 kbyte,
4 kbyte, and 1 kbyte
• Independent Lockdown of TLB Entries
MaverickCrunch
™
Math Engine
The MaverickCrunch Engine is a mixed-mode
coprocessor designed primarily to accelerate the math
processing required to rapidly encode digital audio
formats. It accelerates single and double precision
integer and floating point operations plus an integer
multiply-accumulate (MAC) instruction that is
considerably faster than the ARM920T's native MAC
instruction. The ARM920T coprocessor interface is
utilized thereby sharing its memory interface and
instruction stream. Hardware forwarding and interlock
allows the ARM to handle looping and addressing while
MaverickCrunch handles computation. Features include:
• IEEE-754 single and double precision floating point
• 32 / 64-bit integer
• Add / multiply / compare
• Integer MAC 32-bit input with 72-bit accumulate
• Integer Shifts
• Floating point to/from integer conversion
• Sixteen 64-bit register files
• Four 72-bit accumulators
MaverickKey
™
Unique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP9315 through the use of laser
probing technology. These IDs can then be used to
match secure copyrighted content with the ID of the
target device the EP9315 is powering, and then deliver
the copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
General Purpose Memory Interface (SDRAM,
SRAM, ROM, FLASH)
The EP9315 features a unified memory address model
where all memory devices are accessed over a common
address/data bus. A separate internal port is dedicated to
the read-only Raster/LCD refresh engine, while the rest
of the memory accesses are performed via the Processor
bus. The SRAM memory controller supports 8, 16 and
32-bit devices and accommodates an internal boot ROM
concurrently with 32-bit SDRAM memory.
• 1-4 banks of 32-bit 66 or 100 MHz SDRAM
• One internal port dedicated to the Raster/LCD
Refresh Engine (Read Only)
• Address and data bus shared between SDRAM,
SRAM, ROM, and FLASH memory
• NOR FLASH memory supported
Table B. General Purpose Memory Interface Pin Assignments
Pin Mnemonic Pin Description
SDCLK SDRAM Clock
SDCLKEN SDRAM Clock Enable
SDCSn[3:0] SDRAM Chip Selects 3-0
RASn SDRAM RAS
CASn SDRAM CAS
SDWEn SDRAM Write Enable
CSn[7:6] and CSn[3:0] Chip Selects 7, 6, 3, 2, 1, 0
AD[25:0] Address Bus 25-0
DA[31:0] Data Bus 31-0
DQMn[3:0] SDRAM Output Enables / Data Masks
WRn SRAM Write Strobe
RDn SRAM Read / OE Strobe
WAITn SRAM Wait Input
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

EP9315-IBZ

Mfr. #:
Buy EP9315-IBZ
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Universal Platfrm ARM9 SOC Prcessor
Lifecycle:
New from this manufacturer.
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