1996 Jun 27 25
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
11.2.5 RESET/TOGGLE ENABLE REGISTER (RTE)
Table 26 Reset/Toggle Enable register (address EFH)
Table 27 Description of the RTE bits (note 1)
Note
1. If RTE.n is LOW then P4.n is not affected by a match of CM1 and T2 or CM2 and T2.
For more information, refer to the 8051-based
“8-bit Microcontrollers Data Handbook IC20”
.
76543210
TP47 TP46 RP45 RP44 RP43 RP42 RP41 RP40
BIT SYMBOL FUNCTION
7 TP47 if HIGH then P4.7 toggles on a match of CM2 and T2
6 TP46 if HIGH then P4.6 toggles on a match of CM2 and T2
5 RP45 if HIGH then P4.5 is reset on a match of CM1 and T2
4 RP44 if HIGH then P4.4 is reset on a match of CM1 and T2
3 RP43 if HIGH then P4.3 is reset on a match of CM1 and T2
2 RP42 if HIGH then P4.2 is reset on a match of CM1 and T2
1 RP41 if HIGH then P4.1 is reset on a match of CM1 and T2
0 RP40 if HIGH then P4.0 is reset on a match of CM1 and T2
1996 Jun 27 26
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
11.3 Watchdog Timer (T3)
In addition to Timer T2 and the standard timers (Timer 0
and Timer 1), a Watchdog Timer (WDT) comprising an
11-bit prescaler and an 8-bit timer (T3) is also provided
(see Fig.12).
The timer T3 is incremented every 1.5 ms, derived from
the oscillator frequency of 16 MHz by the following
formula:
When a timer T3 overflow occurs, the microcontroller is
reset and a reset-output-pulse is generated at pin RST.
This short output pulse (3 machine cycles) may be
suppressed if the RST pin is connected to a capacitor.
To prevent a system reset (by an overflow of the WDT), the
user program has to reload T3 within periods that are
shorter than the programmed Watchdog time interval.
If the processor suffers a hardware/software malfunction,
the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the
processor running out of control.
f
timer
f
CLK
12 2048×
--------------------------
=
The Watchdog Timer can only be reloaded if the condition
flag WLE = PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The timer interval between the timer's reloading and the
occurrence of a reset depends on the reloaded value. For
example, this may range from 1.5 ms to 0.375 s when
using an oscillator frequency of 16 MHz.
In the Idle state the Watchdog Timer and reset circuitry
remain active.
The Watchdog Timer (WDT) is controlled by the Enable
Watchdog pin (
EW) (see Table 28).
Table 28
EW controlling WDT and Power-down mode
PIN EW WDT POWER-DOWN MODE
LOW enabled disabled
HIGH disabled enabled
Fig.12 Functional diagram of T3 Watchdog Timer.
h
andbook, full pagewidth
MGA157
INTERNAL BUS
1/12 f
CLK
write
T3
PRESCALER
11-BIT
TIMER T3 (8-BIT)
LOADCLEAR
overflow
internal
reset
LOADEN
EW
LOADEN
PCON.4
PCON.1
CLEAR
WLE PD
R
RST
RST
P
V
DD
INTERNAL BUS
1996 Jun 27 27
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
12 SERIAL I/O PORT: SIO0 (UART)
The Serial Port SIO0 is a full duplex (UART) serial I/O port
i.e. it can transmit and receive simultaneously. This Serial
Port is also receive-buffered. It can commence reception
of a second byte before the previously received byte has
been read from the receive register. However, if the first
byte has still not been read by the time reception of the
second byte is complete, one of these (first or second)
bytes will be lost. The SIO0 receive and transmit registers
are both accessed via the S0BUF SFR. Writing to S0BUF
loads the transmit register, and reading S0BUF accesses
to a physically separate receive register. SIO0 can operate
in 4 modes:
Mode 0 Serial data is transmitted and received through
RXD. TXD outputs the shift clock. 8 data bits are
transmitted/received (LSB first). The baud rate is
fixed at
1
12
of the oscillator frequency.
Mode 1 10 bits are transmitted via TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
and a stop bit (1). On receive, the stop bit is put
into RB8 of the S0CON SFR. The baud rate is
variable.
Mode 2 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9
th
data bit, and a stop bit (1).
On transmit, the 9
th
data bit (TB8 in S0CON) can
be assigned the value of 0 or 1. With nominal
software, TB8 can be the parity bit (P in PSW).
During a receive, the 9
th
data bit is stored in RB8
(S0CON), and the stop bit is ignored. The baud
rate is programmable to either
1
32
or
1
64
of the
oscillator frequency.
Mode 3 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9
th
data bit, and a stop bit (1).
Mode 3 is the same as Mode 2 except for the
baud rate which is variable in Mode 3.
In all four modes, transmission is initiated by any
instruction that writes to the S0BUF SFR.
Reception is initiated in Mode 0 when RI = 0 and REN = 1.
In the other three modes, reception is initiated by the
incoming start bit provided that REN = 1.
Modes 2 and 3 are provided for multiprocessor
communications. In these modes, 9 data bits are received
with the 9
th
bit written to RB8 (S0CON). The 9
th
bit is
followed by the stop bit. The port can be programmed so
that with receiving the stop bit, the Serial Port interrupt will
be activated if, and only if RB8 = 1.
This feature is enabled by setting bit SM2 in S0CON. This
feature may be used in multiprocessor systems.
For more information about how to use the UART in
combination with the registers S0CON, PCON, IE, SBUF
and the Timer register, refer to the 8051-based
“8-bit Microcontrollers Data Handbook IC20”
.
13 SERIAL I/O PORT: SIO1 (CAN)
SIO1 (CAN) provides the CAN (Controller Area Network)
serial-bus data communication interface. SIO1 (CAN)
replaces the SIO1 (I
2
C) serial interface as provided in the
microcontroller derivative P8xC552.
13.1 On-chip CAN-controller
CAN is the definition of a high performance
communication protocol for serial data communication.
The P8xC592 on-chip CAN-controller is a full
implementation of the CAN 2.0A protocol. With the
P8xC592 powerful local networks can be built, both for
automotive and general industrial environments. This
results in a much reduced wiring harness and enhanced
diagnostic and supervisory capabilities.
13.2 CAN Features
Multi-master architecture
Bus access priority determined by the message
identifier
2032 message identifier (2
11
standard frame CAN 2.0A)
Guaranteed latency time for high priority messages
Powerful error handling capability
Data length from 0 up to 8 bytes
Multicast and broadcast message facility
Non destructive bit-wise arbitration
Non-return-to-zero (NRZ) coding/decoding with
bit-stuffing
Programmable transfer rate (up to 1 Mbit/s)
Programmable output driver configuration
Suitable for use in a wide range of networks including
the SAE's network classes A, B and C
DMA providing high-speed on-chip data exchange
Bus failure management facility
1
2
AV
DD
reference voltage.

P80C592FFA/00,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT ROMLESS 68PLCC
Lifecycle:
New from this manufacturer.
Delivery:
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