1996 Jun 27 70
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
16 OSCILLATOR CIRCUITRY
The oscillator circuitry of the P8xC592 is a single-stage
inverting amplifier in a Pierce oscillator configuration. The
circuitry between XTAL1 and XTAL2 is basically an
inverter biased to the transfer point. Either a crystal or
ceramic resonator can be used as the feedback element to
complete the oscillator circuitry. Both are operated in
parallel resonance. XTAL1 (pin 34) is the high gain
amplifier input, and XTAL2 (pin 33) is the output
(see Fig.23). If XTAL1 is driven from an external source,
XTAL2 must be left open (see Fig.24).
Fig.23 P8xC592 oscillator circuit.
handbook, halfpage
C1
XTAL1
XTAL2
20 pF
C2
MLA888
20 pF
34
33
Fig.24 Driving P8xC592 from an external source.
handbook, halfpage
XTAL1
XTAL2
MLA889
external clock
(not TTL compatible)
not connected
34
33
17 RESET CIRCUITRY
The reset pin RST is connected to a Schmitt trigger for
noise rejection (see Fig.25). A reset is accomplished by
holding the RST pin HIGH for at least two machine cycles
(24 oscillator periods). The CPU responds by executing an
internal reset. During reset ALE and PSEN output a HIGH
level. In order to perform a correct reset, this level must not
be affected by external elements.
Also with the P8xC592, the RST line can be pulled HIGH
internally by a pull-up transistor activated by the Watchdog
timer T3. The length of the output pulse from T3 is
3 machine cycles. A pulse of such short duration is
necessary in order to recover from a processor or system
fault as fast as possible.
During Power-down a reset could be generated internally
via the CAN Wake-Up interrupt. Then the RST pin is pulled
HIGH for 6144 machine cycles. In this case the
CAN-controller is not reset.
If the Watchdog timer or the CAN Wake-Up interrupt is
used to reset external devices, the usual capacitor
arrangement for Power-on-reset (see Fig.26) should not
be used.
However, the internal reset is forced, independent of the
external level on the RST pin.
The MAIN RAM and AUXILIARY RAM are not affected.
When V
DD
is turned on, the RAM content is indeterminate.
A reset leaves the internal registers as shown in Table 83.
handbook, halfpage
MGA170 - 1
overflow timer T3
V
DD
RST
on-chip
RST
R
wake-up reset
CAN
CPU
Fig.25 On-chip reset configuration.
