P80C592FFA/00,512 Datasheet P80C592FFA/00,512, P80C592FFA/00,518 | P52-P54

1996 Jun 27 52

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xC592

handbook, full pagewidth

MGA163

SYNCSEG

sample point

(b)

1 clock cycle (t )

SCL

TSEG1

TSEG2

(one bit period)

SYNC.SEG

sample point

(a)

nominal bit time

PROP.SEG PHASE SEG1 PHASE SEG2

transmit point

Fig.18 Bit period.

(a) As defined by the CAN-protocol.

(b) As implemented in the P8xC592's on-chip CAN-controller.

13.5.19.2 Time Segment 1 (TSEG1)

This segment determines the location of the sampling

point within a bit period, which is at the end of TSEG1.

TSEG1 is programmable from 1 to 16 system clock cycles

(see Section 13.5.10).

The correct location of the sample point is essential for the

correct functioning of a transmission. The following points

must be taken into consideration:

• A Start-Of-Frame (see Section 13.6.2) causes all

CAN-controllers to perform a ‘hard synchronization’

(see Section 13.5.20) on the first recessive-to-dominant

edge.

During arbitration, however, several CAN-controllers

may simultaneously transmit. Therefore it may require

twice the sum of bus-line, input comparator and the

output driver delay times until the bus is stable.

This is the propagation delay time.

• To avoid sampling at an incorrect position, it is

necessary to include an additional synchronization

buffer on both sides of the sample point.

The main reasons for incorrect sampling are:

– Incorrect synchronization due to spikes on the

bus-line

– Slight variations in the oscillator frequency of each

CAN-controller in the network, which results in a

phase error.

• Time Segment 1 consists of the segment for

compensation of propagation delays and the

synchronization buffer segment directly before the

sample point (see Fig.18).

1996 Jun 27 53

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xC592

13.5.19.3 Time Segment 2 (TSEG2)

This time segment provides:

• Additional time at the sample point for calculation of the

subsequent bit levels (e.g. arbitration)

• Synchronization buffer segment directly after the

sample point.

TSEG2 is programmable from 1 to 8 system clock cycles

(see Section 13.5.10).

13.5.19.4 Synchronisation Jump Width (SJW)

SJW defines the maximum number of clock cycles (t

SCL

) a

period may be reduced or increased by one

resynchronization. SJW is programmable from 1 to 4

system clock cycles, see Section 13.5.2.

13.5.19.5 Propagation Delay Time (t

prop

)

The Propagation Delay Time is:

prop

is rounded up to the nearest multiple of t

SCL

13.5.19.6 Bit Timing Restrictions

Restrictions on the configuration of the bit timing are based

on internal processing. The restrictions are:

• t

TSEG2

≥ 2t

SCL

• t

TSEG2

≥ t

SJW

• t

TSEG1

≥ t

SEG2

• t

TSEG1

≥ t

SJW

+ t

prop

The three sample mode (SAM = HIGH) has the effect of

introducing a delay of one system clock cycle on the

bus-line. This must be taken into account for the correct

calculation of TSEG1 and TSEG2:

• t

TSEG1

≥ t

SJW

+ t

prop

+ 2t

SCL

• t

TSEG2

≥ 3t

SCL

13.5.20 S

YNCHRONIZATION

Synchronization is performed by a state machine which

compares the incoming edge with its actual bit timing and

adapts the bit timing by hard synchronization or

resynchronization.

prop

2 physical bus delay

input comparator delay

output driver delay

(

)

This type of synchronization occurs only at the beginning

of a message.

The CAN-controller synchronizes on the first incoming

recessive-to-dominant edge of a message (being the

leading edge of a message's Start-Of-Frame bit;

see Section 13.6.2.

Resynchronization occurs during the transmission of a

message's bit stream to compensate for:

• Variations in individual CAN-controller oscillator

frequencies

• Changes introduced by switching from one transmitter

to another (e.g. during arbitration).

As a result of resynchronization either t

TSEG1

may be

increased by up to a maximum of t

SJW

or t

TSEG2

may be

decreased by up to a maximum of t

SJW

• t

TSEG1

≤ t

SCL

[(TSEG1 + 1) + (SJW + 1)]

• t

TSEG2

≥ t

SCL

[(TSEG2 + 1) − (SJW + 1)].

TSEG1, TSEG2 and SJW are the programmed numerical

values.

The phase error (e) of an edge is given by the position of

the edge relative to SYNCSEG, measured in system clock

cycles (t

SCL

The value of the phase error is defined as:

• e = 0, if the edge occurs within SYNCSEG

• e > 0, if the edge occurs within TSEG1

• e < 0, if the edge occurs within TSEG2.

The effect of resynchronization is:

• The same as that of a hard synchronization, if the

magnitude of the phase error (e) is less or equal to the

programmed value of t

SJW

• To increase a bit period by the amount of t

SJW

, if the

phase error is positive and the magnitude of the phase

error is larger than t

SJW

• To decrease a bit period by the amount of t

SJW

, if the

phase error is negative and the magnitude of the phase

error is larger than t

SJW

1996 Jun 27 54

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xC592

13.5.20.1 Synchronization Rules

The synchronization rules are as follows:

• Only one synchronization within one bit time is used.

• An edge is used for synchronization only if the value

detected at the previous sample point differs from the

bus value immediately after the edge.

• Hard synchronization is performed whenever there is a

recessive-to-dominant edge during Bus-Idle

(see Section 13.6.6).

• All other edges (recessive-to-dominant and optionally

dominant-to recessive edges if the Sync bit is set HIGH

(see Section 13.5.3) which are candidates for

resynchronization will be used with the following

exception:

– A transmitting CAN-controller will not perform a

resynchronization as a result of a

recessive-to-dominant edge with positive phase

error, if only these edges are used for

resynchronization. This ensures that the delay times

of the output driver and input comparator do not

cause a permanent increase in the bit time.

13.6 CAN 2.0A Protocol description

13.6.1 F

RAME TYPES

The P8xC592's CAN-controller supports the four different

CAN-protocol frame types for communication:

• Data Frame, to transfer data

• Remote Frame, request for data

• Error Frame, globally signal a (locally) detected error

condition

• Overload Frame, to extend delay time of subsequent

frames (an Overload Frame is not initiated by the

P8xC592 CAN-controller).

13.6.1.1 Bit representation

There are two logical bit representations used in the

CAN-protocol:

• A recessive bit on the bus-line appears only if all

connected CAN-controllers send a recessive bit at that

moment.

• Dominant bits always overwrite recessive bits i.e. the

resulting bit level on the bus-line is dominant.

13.6.2 D

ATA FRAME

A Data Frame carries data from a transmitting

CAN-controller to one or more receiving ones.

A Data Frame is composed of seven different bit-fields:

• Start-Of-Frame

• Arbitration Field

• Control Field

• Data Field (may have a length of zero)

• CRC Field (CRC = Cyclic Redundancy Code)

• Acknowledge Field

• End-Of-Frame.

13.6.2.1 Start-Of-Frame bit

Signals the start of a Data Frame or Remote Frame.

It consists of a single dominant bit use for hard

synchronization of a CAN-controller in receive mode.

13.6.2.2 Arbitration Field

Consists of the message Identifier and the RTR bit. In the

case of simultaneous message transmissions by two or

more CAN-controllers the bus access conflict is solved by

bit-wise arbitration, which is active during the transmission

of the Arbitration Field.

13.6.2.3 Identiﬁer

This 11-bit field is used to provide information about the

message, as well as the bus access priority. It is

transmitted in the order ID.10 to ID.0 (LSB). The situation

that the seven most significant bits (ID.10 to ID.4) are all

recessive must not occur.

An Identifier does not define which particular

CAN-controller will receive the frame because a CAN

based communication network does not differentiate

between a point-to-point, multicast or broadcast

communication.

P80C592FFA/00,512

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Manufacturer:

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IC MCU 8BIT ROMLESS 68PLCC

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