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PCF8533U/2/F2,026

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
PCF8533 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 1 October 2012 16 of 53
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
7.3.3.4 1:4 multiplex drive mode
The 1:4 multiplex drive mode is used when four backplanes are provided in the LCD as
shown in Figure 10
.
V
state1
(t) = V
Sn
(t) V
BP0
(t).
V
on(RMS)
= 0.577V
LCD
.
V
state2
(t) = V
Sn
(t) V
BP1
(t).
V
off(RMS)
= 0.333V
LCD
.
Fig 10. Waveforms for the 1:4 multiplex drive mode with
1
⁄
3
bias
mgl749
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
BP2
(a) Waveforms at driver.
BP3
Sn
Sn+1
Sn+2
Sn+3
T
fr
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
0 V
V
LCD
2V
LCD
/ 3
−2V
LCD
/ 3
V
LCD
/ 3
−V
LCD
/ 3
−V
LCD
0 V
V
LCD
2V
LCD
/ 3
−2V
LCD
/ 3
V
LCD
/ 3
−V
LCD
/ 3
−V
LCD
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
PCF8533 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 1 October 2012 17 of 53
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
7.4 Oscillator
The internal logic and the LCD drive signals of the PCF8533 are timed by a frequency f
clk
,
which either is derived from the built-in oscillator frequency f
osc
or equals an external clock
frequency f
clk(ext)
.
The clock frequency f
clk
determines the LCD frame frequency f
fr
(see Table 14) and is
calculated as follows:
7.4.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to V
SS
. In this case, the output
from pin CLK provides the clock signal for cascaded PCF8533 in the system.
7.4.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to V
DD
.
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.4.3 Timing
The PCF8533 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the synchronization signal (SYNC
) maintains the correct timing relationship
between all PCF8533 in the system. The timing also generates the LCD frame signal (f
fr
)
whose frequency is derived as an integer division of the clock frequency f
clk
(see
Table 14
), applied to pin CLK from either the internal or an external clock.
7.5 Backplane and segment outputs
Table 14. LCD frame frequency
Nominal clock frequency (Hz) LCD frame frequency (Hz)
1536 64
f
clk
f
osc
64
--------
=
f
fr
f
clk
24
--------
=
PCF8533 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 1 October 2012 18 of 53
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
7.5.1 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required, the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode: BP0 and BP2, respectively, BP1 and BP3 carry the same
signals and can also be paired to increase the drive capabilities.
• In static drive mode: The same signal is carried by all four backplane outputs; and
they can be connected in parallel for very high drive requirements.
7.5.2 Segment outputs
The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data residing in the display register. When less
than 80 segment outputs are required, the unused segment outputs must be left
open-circuit.
7.6 Display RAM
The display RAM is a static 80 4 bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 11
, shows rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment
outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second,
third and fourth row of the display RAM are time-multiplexed with BP0,
BP1, BP2, and BP3 respectively.
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PCF8533U/2/F2,026

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Buy PCF8533U/2/F2,026
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers PCF8533U/WLCSP107//2/F2/DIE 2 WAFFLE CARRIERS NDP
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New from this manufacturer.
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