PCF8533 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 1 October 2012 34 of 53
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
[1] Typical output duty cycle of 50 %.
[2] The corresponding frame frequency is .
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
IL
and V
IH
with an
input voltage swing of V
SS
to V
DD
.
Table 21. Dynamic characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 6.5 V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock
f
clk(int)
internal clock frequency
[1][2]
960 1536 3046 Hz
f
clk(ext)
external clock frequency
[1][2]
797 1536 3046 Hz
t
clk(H)
HIGH-level clock time 130 - - s
t
clk(L)
LOW-level clock time 130 - - s
Synchronization: input pin SYNC
t
PD(SYNC_N)
SYNC propagation delay - 30 - ns
t
SYNC_NL
SYNC LOW time 1 - - s
Outputs: pins BP0 to BP3 and S0 to S79
t
PD(drv)
driver propagation delay V
LCD
= 5 V - - 30 s
I
2
C-bus: timing
[3]
; see Figure 25
Pin SCL
f
SCL
SCL clock frequency - - 400 kHz
t
LOW
LOW period of the SCL clock 1.3 - - s
t
HIGH
HIGH period of the SCL clock 0.6 - - s
Pin SDA
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
Pins SCL and SDA
t
BUF
bus free time between a STOP and
START condition
1.3 - - s
t
SU;STO
set-up time for STOP condition 0.6 - - s
t
HD;STA
hold time (repeated) START condition 0.6 - - s
t
SU;STA
set-up time for a repeated START
condition
0.6 - - s
t
r
rise time of both SDA and SCL signals f
SCL
= 400 kHz - - 0.3 s
f
SCL
< 125 kHz - - 1.0 s
t
f
fall time of both SDA and SCL signals - - 0.3 s
C
b
capacitive load for each bus line - - 400 pF
t
w(spike)
spike pulse width on bus - - 50 ns
