PCF8533U/2/F2,026 Datasheet PCF8533U/2/F2,026 | P7-P9

Product data sheet Rev. 6 — 1 October 2012 7 of 53

NXP Semiconductors

PCF8533

Universal LCD driver for low multiplex rates

7.1.5 Command: blink-select

The blink-select command allows configuring the blink mode and the blink frequency.

[1] Only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes.

[2] Default value.

[3] For the blink frequency, see Table 11

7.1.5.1 Blinking

The display blink capabilities of the PCF8533 are very versatile. The whole display can

blink at frequencies selected by the blink-select command (see Table 10

). The blink

frequencies are fractions of the clock frequency. The ratios between the clock and blink

frequencies depend on the blink mode selected (see Table 11

An additional feature is for an arbitrary selection of LCD segments to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. With the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blink frequency. This mode can also be

specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can blink by selectively changing the display RAM data at fixed time

intervals.

Table 10. Blink-select command bit description

See Section 7.1.5.1

Bit Symbol Value Description

7 to 3 - 11110 fixed value

2AB blink mode selection

[1]

[2]

normal blinking

1 blinking by alternating display RAM banks

1 to 0 BF[1:0] blink mode selection

[3]

[2]

off

01 1

10 2

11 3

Table 11. Blink frequencies

Blink mode Normal operating

mode ratio

Nominal blink frequency of f

clk

(typical f

clk

= 1.536 kHz)

Unit

Off - blinking off Hz

12Hz

21Hz

30.5Hz

clk

768

---------

clk

1536

------------

clk

3072

------------

Product data sheet Rev. 6 — 1 October 2012 8 of 53

NXP Semiconductors

PCF8533

Universal LCD driver for low multiplex rates

The entire display can blink at a frequency other than the typical blink frequency. This can

be effectively performed by resetting and setting the display enable bit E at the required

rate using the mode-set command (see Table 6

7.2 Power-On Reset (POR)

At power-on, the PCF8533 resets to the following starting conditions:

1. All backplane outputs are set to V

LCD

2. All segment outputs are set to V

LCD

3. The selected drive mode is: 1:4 multiplex with

⁄

bias.

4. Blinking is switched off.

5. Input and output bank selectors are reset.

6. The I

C-bus interface is initialized.

7. The data pointer and the subaddress counter are cleared (set to logic 0).

8. The display is disabled (bit E = 0, see Table 6

Remark: Do not transfer data on the I

C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.3 Possible display configurations

The display configurations possible with the PCF8533 depend on the required number of

active backplane outputs. A selection of display configurations is given in Table 12

All of the display configurations given in Table 12

can be implemented in a typical system

as shown in Figure 4

Fig 3. Example of displays suitable for PCF8533

7-segment with dot 14-segment with dot and accent

013aaa312

dot matrix

Product data sheet Rev. 6 — 1 October 2012 9 of 53

NXP Semiconductors

PCF8533

Universal LCD driver for low multiplex rates

[1] 7 segment display has 8 elements including the decimal point.

[2] 14 segment display has 16 elements including decimal point and accent dot.

The host microcontroller maintains the 2-line I

C-bus communication channel with the

PCF8533. The internal oscillator is enabled by connecting pin OSC to pin V

. The

appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are the power supplies (V

, and V

LCD

) and the LCD panel chosen for the application.

7.3.1 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three

impedances connected between pins V

LCD

and V

. The center impedance is bypassed

by switch if the

⁄

bias voltage level for the 1:2 multiplex drive mode configuration is

selected.

7.3.2 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

LCD

and the resulting discrimination ratios (D) are given in Table 13.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

Table 12. Selection of possible display configurations

Number of

Backplanes Icons Digits/Characters Dot matrix/

Elements

7-segment

[1]

14-segment

[2]

4 320 40 20 320 (4  80)

3 240 30 15 240 (3  80)

2 160 20 10 160 (2  80)

18010580(1 80)

Fig 4. Typical system configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SDAACK

SCL

OSC

80 segment drives

4 backplanes

LCD PANEL

(up to 320

elements)

PCF8533

A0 A1 A2 SA0

LCD

mgl744

≤

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

PCF8533U/2/F2,026

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NXP Semiconductors

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LCD Drivers PCF8533U/WLCSP107//2/F2/DIE 2 WAFFLE CARRIERS NDP

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