PCF8533 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 1 October 2012 25 of 53
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
8. I
2
C-bus interface
8.1 Characteristics of the I
2
C-bus
The I
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
By connecting pin SDAACK to pin SDA on the PCF8533, the SDA line becomes fully
I
2
C-bus compatible. In COG applications where the track resistance from the SDAACK
pin to the system SDA line can be significant, possibly a voltage divider is generated by
the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a
consequence, it may be possible that the acknowledge generated by the PCF8533 cannot
be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle
is required, it is therefore necessary to minimize the track resistance from the SDAACK
pin to the system SDA line to guarantee a valid LOW level.
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit) design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I
2
C-bus master has to be set up in such a way that it ignores the
acknowledge cycle.
2
The following definition assumes that SDA and SDAACK are connected and refers to the
pair as SDA.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal; see Figure 16
.
8.1.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
2. For further information, please consider the NXP application note: Ref. 1 “AN10170”.
Fig 16. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
