PCF8533 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 1 October 2012 21 of 53
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
7.6.1 Data pointer
The addressing mechanism for the display RAM is realized using a data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 7
). Following this command, an
arriving data byte is stored at the display RAM address indicated by the data pointer. The
filling order is shown in Figure 12
. After each byte is stored, the content of the data pointer
is automatically incremented by a value dependent on the selected LCD drive mode:
• In static drive mode by eight
• In 1:2 multiplex drive mode by four
• In 1:3 multiplex drive mode by three
• In 1:4 multiplex drive mode by two
If an I
2
C-bus data access is terminated early, then the state of the data pointer is
unknown. So, the data pointer must be rewritten before further RAM accesses.
7.6.2 Subaddress counter
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter match with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see Table 8
). If the content of the subaddress counter and
the hardware subaddress do not match, then data storage is inhibited but the data pointer
is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8533 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed while the device is being accessed on the
I
2
C-bus interface.
7.6.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 15 (see Figure 12 as
well).
Table 15. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 and so on, are not connected to any elements on the
display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0 1 2 3 4 5 6 7 8 9 :
0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 :
1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 :
2 a5 a2 - b5 b2 - c5 c2 - d5 :
3 ----------:
