PCF8533 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 1 October 2012 28 of 53
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
The I
2
C-bus protocol is shown in Figure 20. The sequence is initiated with a START
condition (S) from the I
2
C-bus master which is followed by one of two possible PCF8533
slave addresses available. All PCF8533 whose SA0 inputs correspond to bit 0 of the slave
address respond by asserting an acknowledge in parallel. This I
2
C-bus transfer is ignored
by all PCF8533 whose SA0 inputs are set to the alternative level.
After acknowledgement, the control byte is sent defining if the next byte is a RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM or command data (see Figure 21
and Table 18). In this way, it is possible to
configure the device and then fill the display RAM with little overhead.
Fig 20. I
2
C-bus protocol
EXAMPLES
a) transmit two bytes of RAM data
mgl752
S
A
0
S 01110 00
control byte
slave address
RAM/command byte
RAM DATA
M
S
B
L
S
B
A
A
P
R/W = 0
S
A
0
S 01110 0 010
A
A
A
P
RAM DATA
A
b) transmit two command bytes
COMMAND
S
A
0
S 01110 0 100
A
A
A
P
COMMAND
A
A
c) transmit one command byte and two RAM date bytes
COMMAND
S
A
0
S 01110 0 10
00
010
A
A
A
P
RAM DATA
A
RAM DATA
A
A
C
O
R
S
Fig 21. Control byte format
Table 18. Control byte description
Bit Symbol Value Description
7CO continue bit
0 last control byte
1 control bytes continue
6 RS register selection
0 command register
1 data register
5 to 0 - not relevant
mgl753
not relevant
CO
76 543210
RS
MSB LSB
