PCF8533 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 1 October 2012 37 of 53
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8533. This synchronization is guaranteed after the Power-On Reset (POR). The only
time that SYNC
is likely to be needed is if synchronization is accidentally lost (for
example, by noise in adverse electrical environments, or by the definition of a multiplex
mode when PCF8533 with different SA0 levels are cascaded).
SYNC
is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF8533 asserts the SYNC
line at the
onset of its last active backplane signal and monitors the SYNC
line at all other times.
Should synchronization in the cascade be lost, it will be restored by the first PCF8533 to
assert SYNC
. The timing relationships between the backplane waveforms and the SYNC
signal for the various drive modes of the PCF8533 are shown in Figure 27
.
Fig 26. Cascaded PCF8533 configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
CLK
OSC
SYNC
80 segment drives
4 backplanes
80 segment drives
LCD PANEL
(up to 5120
elements)
PCF8533
A0 A1 A2 SA0
V
SS
V
SS
V
SS
V
DD
V
DD
V
LCD
V
LCD
V
DD
V
LCD
mgl754
SDA
SDAACK
SDAACK
SCL
SYNC
CLK
OSC
BP0 to BP3
(open-circuit)
A0 A1 A2 SA0
PCF8533
BP0 to BP3
R
t
r
2C
b
≤
