PCF85162T/1,118 Datasheet PCF85162T/1,118 | P22-P24

Product data sheet Rev. 5 — 17 December 2014 22 of 53

NXP Semiconductors

PCF85162

32 × 4 universal LCD driver for low multiplex rates

7.6.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 8

). Following this command, an

arriving data byte is stored at the display RAM address indicated by the data pointer. The

filling order is shown in Figure 12

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I

C-bus data access terminates early then the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.6.2 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed only when the content of the subaddress counter match with the

hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined

by the device-select command (see Table 9

). If the content of the subaddress counter and

the hardware subaddress do not match then data storage is inhibited but the data pointer

is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

7.6.3 RAM addressing in cascaded applications

In cascaded applications each PCF85162 in the cascade must be addressed separately.

Initially, the first PCF85162 is selected by sending the device-select command matching

the first device's hardware subaddress. Then the data pointer is set to the preferred

display RAM address by sending the load-data-pointer command.

Once the display RAM of the first PCF85162 has been written, the second PCF85162 is

selected by sending the device-select command again. This time however the command

matches the second device's hardware subaddress. Next the load-data-pointer command

is sent to select the preferred display RAM address of the second PCF85162.

This last step is very important because during writing data to the first PCF85162, the data

pointer of the second PCF85162 is incremented. In addition, the hardware subaddress

should not be changed whilst the device is being accessed on the I

C-bus interface.

7.6.4 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 15 (see Figure 12 as

well).

Product data sheet Rev. 5 — 17 December 2014 23 of 53

NXP Semiconductors

PCF85162

32 × 4 universal LCD driver for low multiplex rates

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 16

In the case described in Table 16 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8 etc. have to be connected to segments/elements on the display. This can be

achieved by a combination of writing and rewriting the RAM like follows:

• In the first write to the RAM, bits a7 to a0 are written

• The data-pointer (see Section 7.6.1 on page 22) has to be set to the address of bit a1

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6

• The data-pointer has to be set to the address of bit b1

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some segments/elements remain unused or can be used, but it has to be considered in

the module layout process as well as in the driver software design.

7.6.5 Bank selection

7.6.5.1 Output bank selector

The output bank selector (see Table 10

) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the

particular LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, 2, and then 3

Table 15. Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the

display.

Display RAM

bits (rows)/

backplane

outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

0 1 2 3 4 5 6 7 8 9 :

0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 :

1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 :

2 a5 a2 - b5 b2 - c5 c2 - d5 :

3 ----------:

Table 16. Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.

Display RAM

bits (rows)/

backplane

outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

0 1 2 3 4 5 6 7 8 9 :

0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 :

1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 :

2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 :

3 ----------:

Product data sheet Rev. 5 — 17 December 2014 24 of 53

NXP Semiconductors

PCF85162

32 × 4 universal LCD driver for low multiplex rates

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

The PCF85162 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. In the static drive mode, the bank-select command may request the contents of

row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode,

the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

7.6.5.2 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 10

). The input bank selector functions independently to the output bank selector.

7.6.5.3 RAM bank switching

The PCF85162 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. A bank can be thought of as one RAM row or a collection of RAM rows (see

Figure 13

). The RAM bank switching gives the provision for preparing display information

in an alternative bank and to be able to switch to it once it is complete.

There are two banks; bank 0 and bank 1. Figure 13 shows the location of these banks

relative to the RAM map. Input and output banks can be set independently from one

another with the Bank-select command (see Table 10 on page 7

). Figure 14 shows the

concept.

Fig 13. RAM banks in static and multiplex driving mode 1:2

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PCF85162T/1,118

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NXP Semiconductors

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LCD Drivers I2C - LCD Driver

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