PCF85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 17 December 2014 7 of 53
NXP Semiconductors
PCF85162
32 × 4 universal LCD driver for low multiplex rates
7.1.3 Command: device-select
The device-select command allows defining the subaddress counter value.
[1] Default value.
7.1.4 Command: bank-select
The bank-select command controls where data is written to RAM and where it is displayed
from.
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[2] Default value.
7.1.5 Command: blink-select
The blink-select command allows configuring the blink mode and the blink frequency.
Table 9. Device-select command bit description
See Section 7.6.2.
Bit Symbol Value Description
7C0, 1see Table 6
6 to 3 - 1100 fixed value
2 to 0 A[2:0] 000
[1]
to 111 3 bit binary value, 0 to 7; transferred to the subaddress
counter to define one of eight hardware subaddresses
Table 10. Bank-select command bit description
See Section 7.6.5.
Bit Symbol Value Description
Static 1:2 multiplex
[1]
7 C 0, 1 see Table 6
6 to 2 - 11110 fixed value
1I input bank selection; storage of arriving display data
0
[2]
RAM row 0 RAM rows 0 and 1
1 RAM row 2 RAM rows 2 and 3
0O output bank selection; retrieval of LCD display data
0
[2]
RAM row 0 RAM rows 0 and 1
1 RAM row 2 RAM rows 2 and 3
PCF85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 17 December 2014 8 of 53
NXP Semiconductors
PCF85162
32 × 4 universal LCD driver for low multiplex rates
[1] Default value.
[2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.1.5.1 Blinking
The display blinking capabilities of the PCF85162 are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see Table 11
). The blink
frequencies are derived from the clock frequency. The ratio between the clock and blink
frequencies depends on the blink mode selected (see Table 12
).
An additional feature is for an arbitrary selection of LCD segments/elements to blink. This
applies to the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of
LCD segments/elements can blink by selectively changing the display RAM data at fixed
time intervals.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 7
).
Table 11. Blink-select command bit description
See Section 7.1.5.1.
Bit Symbol Value Description
7C0, 1see Table 6
6 to 3 - 1110 fixed value
2AB blink mode selection
0
[1]
normal blinking
[2]
1 alternate RAM bank blinking
[3]
1 to 0 BF[1:0] blink frequency selection
00
[1]
off
01 1
10 2
11 3
PCF85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 17 December 2014 9 of 53
NXP Semiconductors
PCF85162
32 × 4 universal LCD driver for low multiplex rates
[1] The blink frequency is proportional to the clock frequency (f
clk
). For the range of the clock frequency see
Table 20
.
7.2 Power-On Reset (POR)
At power-on the PCF85162 resets to the following starting conditions:
All backplane and segment outputs are set to V
LCD
The selected drive mode is: 1:4 multiplex with
1
3
bias
Blinking is switched off
Input and output bank selectors are reset
The I
2
C-bus interface is initialized
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled (bit E = 0, see Table 7)
Remark: Do not transfer data on the I
2
C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
Table 12. Blink frequencies
Blink mode Blink frequency equation
[1]
off -
1
2
3
f
blink
f
clk
768
----------
=
f
blink
f
clk
1536
-------------
=
f
blink
f
clk
3072
-------------
=

PCF85162T/1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers I2C - LCD Driver
Lifecycle:
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