PCF85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 17 December 2014 37 of 53
NXP Semiconductors
PCF85162
32 × 4 universal LCD driver for low multiplex rates
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF85162. Synchronization is guaranteed after a power-on reset. The only time that
SYNC
is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex drive mode when PCF85162
with different SA0 levels are cascaded).
SYNC
is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCF85162 asserts the SYNC
line at
the onset of its last active backplane signal and monitors the SYNC
line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF85162 to assert
SYNC
. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF85162 are shown in Figure 27
.
The contact resistance between the SYNC
on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
particularly applicable to chip-on-glass applications. The maximum SYNC
contact
resistance allowed for the number of devices in cascade is given in Table 22
.
The PCF85162 can always be cascaded with other devices of the same type or
conditionally with other devices of the same family. This allows optimal drive selection for
a given number of pixels to display. Figure 24
and Figure 27 show the timing of the
synchronization signals.
(1) Is master (OSC connected to V
SS
).
(2) Is slave (OSC connected to V
DD
).
Fig 26. Cascaded PCF85162 configuration
Table 22. SYNC contact resistance
Number of devices Maximum contact resistance
26 k
3 to 5 2.2 k
6 to 10 1.2 k
10 to 16 700
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