PCF85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 17 December 2014 34 of 53
NXP Semiconductors
PCF85162
32 × 4 universal LCD driver for low multiplex rates
13. Dynamic characteristics
Table 20. Dynamic characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 6.5 V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock
f
clk(int)
internal clock
frequency
[1]
1440 1850 2640 Hz
f
clk(ext)
external clock
frequency
960 - 2640 Hz
f
fr
frame frequency internal clock 60 77 110 Hz
external clock 40 - 110 Hz
t
clk(H)
HIGH-level clock time 60 - - s
t
clk(L)
LOW-level clock time 60 - - s
Synchronization
t
PD(SYNC_N)
SYNC propagation
delay
-30-ns
t
SYNC_NL
SYNC LOW time 1 - - s
t
PD(drv)
driver propagation
delay
V
LCD
= 5 V
[2]
--30s
I
2
C-bus
[3]
Pin SCL
f
SCL
SCL clock frequency - - 400 kHz
t
LOW
LOW period of the
SCL clock
1.3 - - s
t
HIGH
HIGH period of the
SCL clock
0.6 - - s
Pin SDA
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
Pins SCL and SDA
t
BUF
bus free time between
a STOP and START
condition
1.3 - - s
t
SU;STO
set-up time for STOP
condition
0.6 - - s
t
HD;STA
hold time (repeated)
START condition
0.6 - - s
t
SU;STA
set-up time for a
repeated START
condition
0.6 - - s
t
r
rise time of both SDA
and SCL signals
f
SCL
= 400 kHz - - 0.3 s
f
SCL
< 125 kHz - - 1.0 s
PCF85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 17 December 2014 35 of 53
NXP Semiconductors
PCF85162
32 × 4 universal LCD driver for low multiplex rates
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] Not tested in production.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
IL
and V
IH
with an
input voltage swing of V
SS
to V
DD
.
t
f
fall time of both SDA
and SCL signals
--0.3s
C
b
capacitive load for
each bus line
--400pF
t
w(spike)
spike pulse width on the I
2
C-bus - - 50 ns
Table 20. Dynamic characteristics
…continued
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 6.5 V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Fig 24. Driver timing waveforms
Fig 25. I
2
C-bus timing waveforms
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PCF85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 17 December 2014 36 of 53
NXP Semiconductors
PCF85162
32 × 4 universal LCD driver for low multiplex rates
14. Application information
14.1 Cascaded operation
Large display configurations of up to 16 PCF85162 can be recognized on the same
I
2
C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable
I
2
C-bus slave address (SA0).
When cascaded PCF85162 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCF85162 of the cascade contribute
additional segment outputs. The backplanes can either be connected together to enhance
the drive capability or some can be left open-circuit (such as the ones from the slave
in Figure 26
) or just some of the master and some of the slave will be taken to facilitate the
layout of the display.
Table 21. Addressing cascaded PCF85162
Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device
100000
0011
0102
0113
1004
1015
1106
1117
210008
0019
01010
01111
10012
10113
11014
11115

PCF85162T/1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers I2C - LCD Driver
Lifecycle:
New from this manufacturer.
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