PCF85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 17 December 2014 36 of 53
NXP Semiconductors
PCF85162
32 × 4 universal LCD driver for low multiplex rates
14. Application information
14.1 Cascaded operation
Large display configurations of up to 16 PCF85162 can be recognized on the same
I
2
C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable
I
2
C-bus slave address (SA0).
When cascaded PCF85162 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCF85162 of the cascade contribute
additional segment outputs. The backplanes can either be connected together to enhance
the drive capability or some can be left open-circuit (such as the ones from the slave
in Figure 26
) or just some of the master and some of the slave will be taken to facilitate the
layout of the display.
Table 21. Addressing cascaded PCF85162
Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device
100000
0011
0102
0113
1004
1015
1106
1117
210008
0019
01010
01111
10012
10113
11014
11115