Data Sheet ADAU1328
Rev. B | Page 19 of 32
DAISY-CHAIN MODE
The ADAU1328 also allows a daisy-chain configuration to
expand the system to 8 ADCs and 16 DACs (see Figure 18). In
this mode, the DBCLK frequency is 512 f
S
. The first eight slots
of the DAC TDM data stream belong to the first ADAU1328 in
the chain and the last eight slots belong to the second ADAU1328.
The second ADAU1328 is the device attached to the DSP
TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
ADAU1328 can be configured into a dual-line, DAC TDM
mode, as shown in Figure 19. This mode allows a slower
DBCLK than normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first ADAU1328 in the chain and the last four channels belong
to the second ADAU1328.
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the ADAU1328, as shown in Figure 20.
There are two configurations for the ADC port to work in
daisy-chain mode. The first one is with an ABCLK at 256 f
S
shown in Figure 21. The second configuration is shown in
Figure 22. Note that in the 512 f
S
ABCLK mode, the ADC
channels occupy the first eight slots; the second eight slots are
empty. The TDM_IN of the first ADAU1328 must be grounded
in all modes of operation.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 12 for a detailed description of
the function of each pin. See Figure 26 for a typical ADAU1328
configuration with two external stereo DACs and two external
stereo ADCs.
Figure 23 through Figure 25 show the serial mode formats. For
maximum flexibility, the polarity of LRCLK and BCLK are
programmable. In these figures, all of the clocks are shown with
their normal polarity. The default mode is I
2
S.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
DSDATA1 (TDM_IN)
OF THE SECOND ADAU1328
DSDATA2 (TDM_OUT)
OF THE SECOND ADAU1328
THIS IS THE TDM
TO THE FIRST ADAU1328
DAC L1
DAC R1 DAC L2 DAC R2
DAC L3 DAC R3 DAC L4
DAC R4 DAC L1
DAC R1 DAC L2
DAC R2 DAC L3
DAC R3 DAC L4
DAC R4
DAC L1 DAC R1 DAC L2
DAC R2 DAC L3 DAC R3
DAC L4 DAC R4
32 BITS
DSP
SECOND
ADAU1328
FIRST
ADAU1328
06102-054
Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two ADAU1328 Daisy Chain)
