Data Sheet ADAU1328
Rev. B | Page 29 of 32
ADDITIONAL MODES
The ADAU1328 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 27 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configuration
is applicable when the ADAU1328 master clock is generated by
the PLL with the DLRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the ADAU1328
in cases of high speed TDM data transmission, the ADAU1328
can latch in the data using the falling edge of DBCLK. This
effectively dedicates the entire BCLK period to the setup time.
This mode is useful in cases where the source has a large delay
time in the serial data driver. Figure 28 shows this pipeline
mode of data transmission.
Both the BLCK-less and pipeline modes are available on the
ADC serial data port.
DLRCLK
INTERNAL
DBCLK
DSDATA
DLRCLK
INTERNAL
DBCLK
TDM-DSDATA
32 BITS
06102-059
Figure 27. Serial DAC Data Transmission in TDM Format Without DBCLK
(Applicable Only If PLL Locks to DLRCLK. This Mode Is Also Available in the ADC Serial Data Port)
DLRCLK
DBCLK
DSDATA
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
06102-060
Figure 28. I
2
S Pipeline Mode in DAC Serial Data Transmission
(Applicable in Stereo and TDM Useful for High Frequency TDM Transmission.
This Model Is Also Available in the ADC Serial Data Port.)
