ADAU1328 Data Sheet
Rev. B | Page 24 of 32
CONTROL REGISTERS
DEFINITIONS
The global address for the ADAU1328 is 0x04, shifted left 1 bit due to the R/
W
bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 13. Register Format
Global Address R/
W
Register Address Data
Bit
23:17 16 15:8 7:0
Table 14. Register Addresses and Functions
Address Function
0 PLL and Clock Control 0
1 PLL and Clock Control 1
2 DAC Control 0
3 DAC Control 1
5 DAC individual channel mutes
6 DAC 1L volume control
7 DAC 1R volume control
8 DAC 2L volume control
9 DAC 2R volume control
10 DAC 3L volume control
11 DAC 3R volume control
12 DAC 4L volume control
13 DAC 4R volume control
14 ADC Control 0
15 ADC Control 1
16 ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 15. PLL and Clock Control 0
Bit Value Function Description
0 0 Normal operation PLL power-down
1 Power-down
2:1 00 INPUT 256 (×44.1 kHz or 48 kHz) MCLK pin functionality (PLL active)
01 INPUT 384 (×44.1 kHz or 48 kHz)
10 INPUT 512 (×44.1 kHz or 48 kHz)
11 INPUT 768 (×44.1 kHz or 48 kHz)
4:3 00 XTAL oscillator enabled MCLKO pin
01 256 × f
S
VCO output
10 512 × f
S
VCO output
11 Off
6:5 00 MCLK PLL input
01 DLRCLK
10 ALRCLK
11 Reserved
7 0 Disable: ADC and DAC idle Internal MCLK enable
1 Enable: ADC and DAC active
