ADAU1328 Data Sheet
Rev. B | Page 30 of 32
APPLICATION CIRCUITS
Typical applications circuits are shown in Figure 29 through
Figure 32. Figure 29 shows a typical ADC input filter circuit.
Recommended loop filters for LR clock and master clock as the
PLL reference are shown in Figure 30. Output filters for the
DAC outputs are shown in Figure 31 and Figure 32 for the
noninverting and inverting cases, respectively.
2
1
3
OP275
–
+
6
7
5
OP275
–
+
5.76kΩ
5.76kΩ 237Ω
5.76kΩ
120pF
600Z
AUDIO
INPUT
100pF
5.76kΩ
120pF
4.7µF
+
237Ω
4.7µF
+
100pF
1nF
NPO
1nF
NPO
ADCxN
ADCxP
06102-023
Figure 29. Typical ADC Input Filter Circuit
39nF
+
2.2nF
LF
LRCLK
AVDD2
3.32kΩ
5.6nF
390nF
LF
MCLK
AVDD2
562Ω
06102-027
Figure 30. Recommended Loop Filters for LRCLK or MCLK PLL Reference
3
1
2
OP275
+
–
4.75kΩ4.75kΩ
4.7µF
+
DAC OUT
240pF
NPO
270pF
NPO
3.3nF
NPO
AUDIO
OUTPUT
4.99kΩ
604Ω
4.99kΩ
49.9kΩ
06102-024
Figure 31. Typical DAC Output Filter Circuit (Single-Ended, Noninverting)
2
1
3
OP275
–
+
3.01kΩ
11kΩ
4.7µF
+
DAC
OUT
CM
0.1µF
270pF
NPO
68pF
NPO
2.2nF
NPO
AUDIO
OUTPUT
604Ω
49.9kΩ
11kΩ
06102-025
Figure 32. Typical DAC Output Filter Circuit (Single-Ended, Inverting)
