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ADAU1328BSTZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
Data Sheet ADAU1328
Rev. B | Page 21 of 32
ALRCLK
ABCLK
4 ADC CHANNELS OF
SECOND IC IN THE CHAIN
4 ADC CHANNELS OF
FIRST IC IN THE CHAIN
ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2
ASDATA1 (TDM_OUT
OF THE SECOND ADAU1328
IN THE CHAIN)
ADC L1 ADC R1 ADC L2 ADC R2
ASDATA2 (TDM_IN
OF THE SECOND ADAU1328
IN THE CHAIN)
32 BITS
MSB
DSP
SECOND
ADAU1328
FIRST
ADAU1328
06102-057
Figure 22. Dual-Line ADC TDM Daisy-Chain Mode (512 f
S
ABCLK, Two ADAU1328 Daisy Chain)
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LSB LSB
LSB
LSB
LSB LSB
LEFT CHANNEL RIGHT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LEFT CHANNEL RIGHT CHANNEL
MSB MSB
MSB
MSB
MSB MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I
2
S MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDATA LSB LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT f
S
EXCEPT FOR DSP MODE, WHICH IS 2 ×f
S
.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB MSB
1/f
S
06102-013
Figure 23. Stereo Serial Modes
ADAU1328 Data Sheet
Rev. B | Page 22 of 32
DBCLK
DLRCLK
DSDATA
LEFT-JUSTIFIED
MODE
DSDATA
RIGHT-JUSTIFIED
MODE
DSDATA
I
2
S-JUSTIFIED
MODE
t
DLH
t
DBH
t
DBL
t
DLS
t
DDS
MSB
MSB
MSB
LSB
MSB–1
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
t
DDH
t
DDS
06102-014
Figure 24. DAC Serial Timing
ABCLK
ALRCLK
ASDATA
LEFT-JUSTIFIED
MODE
ASDATA
RIGHT-JUSTIFIED
MODE
ASDATA
I
2
S-JUSTIFIED
MODE
t
ABH
LSB
MSB
MSB
MSB
MSB–1
t
ABL
t
ALS
t
ABDD
t
ABDD
t
ABDD
t
ALH
06102-015
Figure 25. ADC Serial Timing
Data Sheet ADAU1328
Rev. B | Page 23 of 32
Table 12. Pin Function Changes in TDM and AUX Modes (Replication of Table 11)
Mnemonic Stereo Modes TDM Modes AUX Modes
ASDATA1 ADC1 Data Out ADC TDM Data Out TDM Data Out
ASDATA2 ADC2 Data Out ADC TDM Data In AUX Data Out 1 (to External DAC 1)
DSDATA1 DAC1 Data In DAC TDM Data In TDM Data In
DSDATA2 DAC2 Data In DAC TDM Data Out AUX Data In 1 (from External ADC 1)
DSDATA3 DAC3 Data In DAC TDM Data In 2 (Dual-Line Mode) AUX Data In 2 (from External ADC 2)
DSDATA4 DAC4 Data In DAC TDM Data Out 2 (Dual-Line Mode) AUX Data Out 2 (to External DAC 2)
ALRCLK ADC LRCLK In/Out ADC TDM Frame Sync In/Out TDM Frame Sync In/Out
ABCLK ADC BCLK In/Out ADC TDM BCLK In/Out TDM BCLK In/Out
DLRCLK DAC LRCLK In/Out DAC TDM Frame Sync In/Out AUX LRCLK In/Out
DBCLK DAC BCLK In/Out DAC TDM BCLK In/Out AUX BCLK In/Out
AUX
ADC 1
LRCLK
BCLK
DATA
MCLK
AUX
ADC 2
LRCLK
BCLK
DATA
MCLK
AUX
DAC 1
AUX
DAC 2
LRCLK
BCLK
DATA
MCLK
LRCLK
BCLK
DATA
MCLK
30MHz
12.288MHz
SHARC IS RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
SHARC
ADAU1328
TDM MASTER
AUX MASTER
FSYNC-TDM (RFS)
RxCLK
RxDATA
TxCLK
TxDATA
TFS (NC)
ASDATA2
DSDATA4
DBCLK
DLRCLK
DSDATA2
DSDATA3
MCLK
ASDATA1
ALRCLK ABCLK DSDATA1
06102-019
Figure 26. Example of AUX Mode Connection to SHARC® (ADAU1328 as TDM Master/AUX Master Shown)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

ADAU1328BSTZ-RL

Mfr. #:
Buy ADAU1328BSTZ-RL
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs 2 ADC/8 DAC w/ PLL 192kHz 24B
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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