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ADV212BBCZ-150

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
ADV212
Rev. B | Page 12 of 44
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter Mnemonic Min Typ Max Unit
DREQ Pulse Width
1
DREQ
PULSE
1 JCLK
2
15 JCLK
2
ns
WE to DREQ Deassert (DR × PULS = 0)
t
DREQ
RTN
2.5 JCLK
2
3.5 × JCLK + 7.5
2
ns
DACK to WE Setup
t
DACK
SU
0 ns
Data Setup t
SU
2.5 ns
Data Hold t
HD
2 ns
WE Assert Pulse Width WE
LOW
1.5 JCLK
2
ns
WE Deassert Pulse Width WE
HIGH
1.5 JCLK
2
ns
WE Deassert to Next DREQ
t
DREQ
WAIT
2.5 JCLK
2
4.5 × JCLK + 9.0
2
ns
WE Deassert to DACK Deassert
t
WE_DACK
0 ns
1
Applies to assigned DMA channel, if EDMOD0/EDMOD1[14:11] is programmed to a nonzero value.
2
For a definition of JCLK, see Figure 32.
DREQ
DACK
WE
HDATA
WE
HIGH
WE
LOW
t
DACK
SU
t
HD
t
SU
0 1 13
14 15
t
DREQ
WAIT
DREQ
PULSE
t
WE_DACK
06389-022
Figure 13. Burst Write Cycle for
DREQ
/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:1] Not Programmed to a Value of 0000)
Figure 14. Burst Write Cycle for
DREQ
/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
Figure 15. Burst Write Cycle for Fly-By DMA Mode
ADV212
Rev. B | Page 13 of 44
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter Mnemonic Min Typ Max Unit
DREQ Pulse Width
1
DREQ
PULSE
1 JCLK
2
15 JCLK
2
ns
RD to DREQ Deassert (DR × PULS = 0)
t
DREQ
RTN
2.5 JCLK
2
3.5 × JCLK + 7.5
2
ns
DACK to RD Setup
t
DACK
SU
0 ns
RD to Data Valid
t
RD
2.5 9.7 ns
Data Hold t
HD
2.5 ns
RD Assert Pulse Width
RD
LOW
1.5 JCLK
2
ns
RD Deassert Pulse Width
RD
HIGH
1.5 JCLK
2
ns
RD Deassert to Next DREQ
t
DREQ
WAIT
2.5 JCLK
2
3.5 × JCLK + 7.5
2
ns
RD Deassert to DACK Deassert
t
RD_DACK
0 ns
1
Applies to assigned DMA channel if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
2
For a definition of JCLK, see Figure 32.
Figure 16. Burst Read Cycle for
DREQ
/
DACK
DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1[14:11] Not Programmed to a Value of 0
Figure 17. Burst Read Cycle for
DREQ
/
DACK
DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
DREQ
DACK
RDFB
t
DACK
SU
t
HD
t
DREQ
WAIT
HDATA
0 1 13 14 15
t
RD
t
DREQ
RTN
t
RD_DACK
06389-027
Figure 18. Burst Read Cycle for Fly-By DMA Mode
ADV212
Rev. B | Page 14 of 44
STREAMING MODE (JDATA)—FIFO READ/WRITE
Table 10.
Parameter Mnemonic Min Typ Max Unit
MCLK to JDATA Valid JDATA
TD
1.5 JCLK
1
2.5 × JCLK + 9.5
1
ns
MCLK to VALID Assert/Deassert VALID
TD
1.5 JCLK
1
2.5 × JCLK + 8.0
1
ns
HOLD Setup to Rising MCLK HOLD
SU
3 ns
HOLD Hold from Rising MCLK HOLD
HD
3 ns
JDATA Setup to Rising MCLK JDATA
SU
3 ns
JDATA Hold from Rising MCLK JDATA
HD
3 ns
1
For a definition of JCLK, see Figure 32.
MCLK
JDATA
VALID
HOLD
HOLD
HD
HOLD
SU
VALID
TD
JDATA
SU
JDATA
TD
JDATA
HD
06389-028
Figure 19. Streaming Mode Timing—Encode Mode JDATA Output
MCLK
JDATA
VALID
HOLD
HOLD
HD
HOLD
SU
VALID
TD
JDATA
SU
JDATA
HD
06389-029
Figure 20. Streaming Mode Timing—Decode Mode JDATA Input
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

ADV212BBCZ-150

Mfr. #:
Buy ADV212BBCZ-150
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 CODEC w/Integrated Controller
Lifecycle:
New from this manufacturer.
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