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ADV212BBCZ-150

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
ADV212
Rev. B | Page 3 of 44
The ADV212 can process images at a rate of 40 MSPS in
reversible mode and at higher rates when used in irreversible
mode. The ADV212 contains a dedicated wavelet transform
engine, three entropy CODECs, an on-board memory system,
and an embedded reduced instruction set computer (RISC)
processor that can provide a complete JPEG2000 compression/
decompression solution.
The wavelet processor supports the 9/7 irreversible wavelet
transform and the 5/3 wavelet transform in reversible and
irreversible modes. The entropy CODECs support all features
in the JPEG2000 Part 1 specification except maximum shift
region of interest (ROI).
The ADV212 operates on a rectangular array of pixel samples
called a tile. A tile can contain a complete image, up to the
maximum supported size, or some portion of an image. The
maximum horizontal tile size supported depends on the wavelet
transform selected and the number of samples in the tile.
Images larger than the ADV212 maximum tile size can be
broken into individual tiles and then sent sequentially to the
chip while maintaining a single, fully compliant JPEG2000 code
stream for the entire image.
JPEG2000 FEATURE SUPPORT
The ADV212 supports a broad set of features that are included
in Part 1 of the JPEG2000 standard (ISO/IEC 15444).
Depending on the particular application requirements, the
ADV212 can provide varying levels of JPEG2000 compression
support. It can provide raw code block and attribute data
output, which allows the host software to have complete control
over generation of the JPEG2000 code stream and other aspects
of the compression process such as bit-rate control.
Additionally, the ADV212 can create a complete, fully
compliant JPEG2000 code stream (J2C) and enhanced file
formats such as JP2.
FUNCTIONAL BLOCK DIAGRAM
PIXEL I/F
EXTERNAL
DMA CTRL
WAVELET
ENGINE
INTERNAL BUS AND DMA ENGINE
PIXEL I/F
EC1 EC2 EC3
EMBEDDED
RISC
PROCESSOR
SYSTEM
RAM
ROM
ADV212
CODE FIFO
PIXEL FIFO
ATTR FIFO
HOST I/F
06389-001
Figure 1.
ADV212
Rev. B | Page 4 of 44
SPECIFICATIONS
Specifications apply to IOVDD = 2.5 V or 3.3 V over the operating temperature range, unless otherwise specified.
SUPPLY VOLTAGES AND CURRENT
Table 1.
Parameter Mnemonic Min Typ Max Unit
DC Supply Voltage, Core V
DD
1.425 1.5 1.575 V
DC Supply Voltage, Input/Output IOVDD 2.375 2.5 2.625 V
IOVDD 3.135 3.3 3.465 V
Input Range V
IN
−0.3 V
DDI/O
+ 0.3 V
Operating Ambient Temperature Range in Free Air T −40 +25 +85 °C
Static Current
1
I
DD
60
mA
Dynamic Current, Core (JCLK
2
Frequency = 150 MHz)
3
380 440 mA
Dynamic Current, Core (JCLK
2
Frequency = 108 MHz) 280 320 mA
Dynamic Current, Core (JCLK
2
Frequency = 81 MHz) 210 290 mA
Dynamic Current, Input/Output 40 50 mA
1
No clock or input/output activity.
2
For a definition of JCLK, see Figure 32.
3
ADV212-150 only.
INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter Mnemonic Min Typ Max Unit Test Conditions
High Level Input Voltage V
IH (3.3 V)
2.2 V V
DD
= maximum
V
IH (2.5 V)
1.9 V V
DD
= maximum
Low Level Input Voltage V
IL (3.3 V, 2.5 V)
0.6 V V
DD
= minimum
High Level Output Voltage V
OH (3.3 V)
2.4 V V
DD
= minimum, I
OH
= −0.5 mA
V
OH (2.5 V)
2.0 V V
DD
= minimum, I
OH
= −0.5 mA
Low Level Output Voltage V
OL (3.3 V, 2.5 V)
0.4 V V
DD
= minimum, I
OL
= +2 mA
High Level Input Current I
IH
1.0 µA V
DD
= maximum, V
IN
= V
DD
Low Level Input Current I
IL
1.0 µA V
DD
= maximum, V
IN
= 0 V
High Level Three-State Leakage Current I
OZH
1.0 µA V
DD
= maximum, V
IN
= V
DD
Low Level Three-State Leakage Current I
OZL
1.0 µA V
DD
= maximum, V
IN
= 0 V
Input Pin Capacitance C
I
8 pF
Output Pin Capacitance C
O
8 pF
ADV212
Rev. B | Page 5 of 44
CLOCK AND RESET SPECIFICATIONS
Table 3.
Parameter Mnemonic Min Typ Max Unit
MCLK Period t
MCLK
13.3 100 ns
MCLK Frequency f
MCLK
10 75.18 MHz
MCLK Width Low t
MCLKL
6 ns
MCLK Width High t
MCLKH
6 ns
VCLK Period t
VCLK
13.4 50 ns
VCLK Frequency f
VCLK
20 74.60 MHz
VCLK Width Low t
VCLKL
5 ns
VCLK Width High t
VCLKH
5 ns
RESET Width Low
t
RESET
5 MCLK cycles
1
1
For a definition of MCLK, see Figure 32.
MCLK
VCLK
t
MCLK
t
MCLKH
t
MCLKL
t
VCLKH
t
VCLKL
t
VCLK
06389-010
Figure 2. Input Clock
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

ADV212BBCZ-150

Mfr. #:
Buy ADV212BBCZ-150
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 CODEC w/Integrated Controller
Lifecycle:
New from this manufacturer.
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