ADV212
Rev. B | Page 20 of 44
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A
B
C
D
E
F
G
J
H
K
L
10 8 7 6 3 2 19 5 411
BOTTOM VIEW
(Not to Scale)
06389-035
Figure 30.121-Ball Pin Configuration
A
B
C
D
E
F
G
J
H
K
L
M
12
11
10 8
7
6
3
2
1
9
5
4
BOTTOM VIEW
(Not to Scale)
06389-036
Figure 31. 144-Ball Pin Configuration
Table 16. Pin Function Descriptions
121-Ball Package 144-Ball Package
Pin No. Location Pin No. Location Mnemonic
Pins
Used Type Description
119 L9 132 L12 MCLK 1 I
System Input Clock. See the PLL Registers
section.
117 L7 131 L11
RESET
1 I
Reset. Causes the ADV212 to immediately reset.
CS
, RD, WE, DACK0, DACK1, DREQ0, and DREQ1
must be held high when a RESET
is applied.
37 to 34,
27 to 25,
16, 15, 24,
14 to 12,
2, 6, 5
D4 to D1,
C5 to C3,
B5, B4, C2,
B3 to B1,
A2, A6, A5
64, 49 to
51, 37 to
39, 25 to
27, 13 to
15, 2 to 4
F4, E1 to E3,
D1 to D3,
C1 to C3,
B1 to B3,
A2 to A4
HDATA[15:0]
16
I/O
Host Data Bus. With HDATA[23:16],
HDATA[27:24], and HDATA[31:28], these pins
make up the 32-bit wide host data bus. The
async host interface is interfaced together
with ADDR[3:0], CS
, WE, RD, and ACK.
Unused HDATA pins should be pulled down
via a 10 kΩ resistor.
88, 107,
87, 97
H11, K8,
H10, J9
108 to 106,
96
J12 to J10,
H12
ADDR[3:0]
4
I
Address Bus for the Host Interface.
96 J8 95 H11
CS
1 I
Chip Select. This signal is used to qualify
addressed read and write access to the
ADV212 using the host interface.
95 J7 94 H10
WE
1
1 I Write Enable Used with the Host Interface.
RDFB
2
Read Enable When Fly-By DMA Is Enabled.
Simultaneous assertion of WE
and DACK low
activates the HDATA bus, even if the DMA
channels are disabled.
86 H9 84 G12
RD
1
1 I Read Enable Used with the Host Interface.
WEFB
3
Write Enable When Fly-By DMA Is Enabled.
Simultaneous assertion of RD
and DACK low
activates the HDATA bus, even if the DMA
channels are disabled.
