ADV212
Rev. B | Page 36 of 44
DIGITAL STILL CAMERA/CAMCORDER
Figure 35 is a typical configuration for a digital camera or camcorder.
D[9:0]
10
DATA INPUTS[9:0]
MCLK
VCLK
VFRM
VRDY
VSTRB
VDATA[15:6]PIXEL OUT[9:0]
SDATA SERIAL DATA
SCK SERIAL CLK
SL SERIAL EN
AD9843A
FPGA
16-BIT
HOST CPU
ADV212
DATA[15:0]HDATA[15:0]
ADDR[3:0]ADDR[3:0]
CSCS
RDRD
WEWE
ACK
ACK
IRQIRQ
06389-004
Figure 35. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode
ADV212
Rev. B | Page 37 of 44
ENCODE/DECODE SDTV VIDEO APPLICATION
Figure 36 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode.
ENCODE MODE
32-BIT
HOST CPU
ADV212
HDATA[31:0]DATA[31:0]
10-BIT
VIDEO
DECODER
IRQINTR
ADDR[3:0]ADDR[3:0]
P[19:10]VDATA[11:2]
VIDEO IN
LLC1
MCLK
27MHz
OSC
VCLK
CS
CS
RD
RD
WEWE
ACKACK
27MHz
OSC
DECODE MODE
32-BIT
HOST CPU
ADV212
HDATA[31:0]DATA[31:0]
10-BIT
VIDEO
ENCODER
IRQINTR
ADDR[3:0]ADDR[3:0]
P[9:0]VDATA[11:2]
VIDEO OUT
CLKINVCLK
MCLK
CS
CS
RD
RD
WEWE
ACKACK
06389-005
Figure 36. Encode/DecodeSDTV Video Application
ADV212
Rev. B | Page 38 of 44
32-BIT HOST APPLICATION
Figure 37 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode.
ENCODE MODE
32-BIT
HOST CPU
ADV212
DATA[31:0]
IRQIRQ
ADDR[3:0]
ADDR[3:0]
CSCS
RDRD
WEWE
ACK
ACK
FPGA
ADV7189
10-BIT
VIDEO
DECODER
P[19:10]
LLC1
V
DATA[11:2]
VIDEO IN
VCLK
MCLK
DREQ0DREQ0
DACK0DACK0
HDATA[31:0]DATA[31:0]
27MHz
OSC
27MHz
OSC
DECODE MODE
31-BIT
HOST CPU
ADV212
DATA[31:0]
IRQIRQ
ADDR[3:0]ADDR[3:0]
CSCS
RDRD
WEWE
ACKACK
FPGA
10-BIT
VIDEO
ENCODER
P[9:0]VDATA[11:2]
VIDEO OUT
CLKINVCLK
MCLK
DREQ0DREQ0
DACK0DACK0
HDATA[31:0]DATA[31:0]
06389-006
Figure 37. Encode/Decode 32-Bit Host Application

ADV212BBCZ-150

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 CODEC w/Integrated Controller
Lifecycle:
New from this manufacturer.
Delivery:
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