ADV212
Rev. B | Page 34 of 44
APPLICATIONS INFORMATION
This section describes typical video applications for the
ADV212 JPEG2000 video processor.
ENCODE—MULTICHIP MODE
Due to the data input rate limitation (see Table 22), an 1080i
application requires at least two ADV212s to encode or decode
full-resolution 1080i video. In encode mode, the ADV212
accepts Y and CbCr data on separate buses. An encode example
is shown in Figure 33.
In decode mode, a master/slave configuration (as shown in
Figure 34) or a slave/slave configuration can be used to
synchronize the outputs of the two ADV212s.
Applications that have two separate VDATA outputs sent to an
FPGA or buffer before they are sent to an encoder do not
require synchronization at the ADV212 outputs.
DATA[31:0] HDATA[31:0]
ADDR[3:0] ADDR[3:0]
CS CS
RD RD
WR
WE
ACK
ACK
IRQ
CS
RD
WR
ACK
IRQ
DREQ
DACK
IRQ
DREQ DREQ
FIELD
VSYNC
HSYNC
DACK DACK
GPIO SCOMM[5]
VCLK
1080i
VIDEO IN
MCLK
VDATA[11:2]
32-BIT HOST CPU
10-BIT SD/HD
VIDEO
DECODER
ADV212_1_SLAVE
SCOMM[5]
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
FIELD
VSYNC
HSYNC
DREQ
DACK
VCLK
MCLK
VDATA[11:2]
ADV212_2_SLAVE
LLC
Y[9:0]
C[9:0]
CbCr
CbCr
Y
74.25MHz
OSC
06389-002
Figure 33. Encode—Multichip Application
