ADV212
Rev. B | Page 39 of 44
HIPI (HOST INTERFACEPIXEL INTERFACE)
Figure 38 is a typical configuration using HIPI mode.
HDATA<31>Y0/G0<MSB>
HDATA<30>Y0/G0<6>
HDATA<29>Y0/G0<5>
HDATA<28>Y0/G0<4>
HDATA<27>Y0/G0<3>
HDATA<26>Y0/G0<2>
HDATA<25>Y0/G0<1>
HDATA<24>Y0/G0<0>
HDATA<23>Cb0/G1<MSB>
HDATA<22>Cb0/G1<6>
HDATA<21>Cb0/G1<5>
HDATA<20>Cb0/G1<4>
HDATA<19>Cb0/G1<3>
HDATA<18>Cb0/G1<2>
HDATA<17>Cb0/G1<1>
HDATA<16>Cb0/G1<0>
HDATA<15>Y1/G2<MSB>
HDATA<14>Y1/G2<6>
HDATA<13>Y1/G2<5>
HDATA<12>Y1/G2<4>
HDATA<11>Y1/G2<3>
HDATA<10>Y1/G2<2>
HDATA<9>Y1/G2<1>
HDATA<8>Y1/G2<0>
HDATA<7>Cr0/G3<MSB>
HDATA<6>Cr0/G3<6>
HDATA<5>Cr0/G3<5>
HDATA<4>Cr0/G3<4>
HDATA<3>Cr0/G3<3>
HDATA<2>Cr0/G3<2>
HDATA<1>Cr0/G3<1>
HDATA<0>Cr0/G3<0>
CS
DATA<31:0>
CS
RD RD
WR
WE
ACK
ACK
IRQ IRQ
DREQ DREQ0
DACK DACK0
MCLK
74.25MHz
DREQ DREQ1
DACK
DACK1
ADV212
32-BIT HOST
COMPRESSED
DATA PATH
RAW PIXEL
DATA PATH
06389-007
Figure 38. Host InterfacePixel Interface Mode
ADV212
Rev. B | Page 40 of 44
JDATA INTERFACE
Figure 39 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR 656.
16-BIT
HOST CPU
FPGA
ADV212
HDATA[15:0]DATA[15:0]
ADV7189
IRQIRQ
ADDR[3:0]ADDR[3:0]
P[19:10]VDATA[11:2]
FIELDFIELD
VSVSYNC
HS
LLC1
HSYNC
MCLK
27MHz
OSC
VCLK
VIDEO IN
YCrCb
CSCS
JDATA[7:0]
HOLD
VALID
RD
RD
WE
WE
ACKACK
06389-008
Figure 39. JDATA Application
ADV212
Rev. B | Page 41 of 44
OUTLINE DIMENSIONS
*COMPLIANT WITH JEDEC STANDARDS MO-192-ABD-1 WITH
EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
DETAIL A
0.70
0.60
0.50
BALL DIAMETER
0.20
COPLANARITY
1.00
BSC
10.00
BSC SQ
A
B
C
D
E
F
G
H
J
K
L
10
8
7
6
3
2
1
9
5
4
11
*
1.31
1.21
1.11
A1 CORNER
INDEX AREA
TOP VIEW
BALL A1
CORNER
DETAIL A
BOTTOM VIEW
0.50 NOM
0.30 MIN
*
1.85
1.71
1.40
12.20
12.00 SQ
11.80
082406-A
SEATING
PLANE
Figure 40. 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-121-1)
Dimensions shown in millimeters
SEATING
PLANE
DETAIL A
0.70
0.60
0.50
BALL DIAMETER
COPLANARITY
0.20 MAX
1.00 BSC
11.00
BCS SQ
A
B
C
D
E
F
G
J
H
K
L
M
12
11
10 8
7
6
3
2
1
9
5
4
0.53
0.43
A1 CORNER
INDEX AREA
TOP VIEW
13 .00
BSC SQ
BALL A1
INDICATOR
DETAIL A
BOTTOM VIEW
*
1.85
MAX
*
1.32
1.21
1.11
*
COMPLIANT WITH JEDEC STANDARDS MO-192-AAD-1 WITH
EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
021506-A
Figure 41. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-3)
Dimensions shown in millimeters

ADV212BBCZ-150

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 CODEC w/Integrated Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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