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ADV212BBCZ-150
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
ADV212
Rev.
B
| Page
39
of
44
HIPI (HOST INTERFA
CE
—
PIXEL INTER
FACE)
Fig
ure
38
is a typical conf
iguration using H
IPI mode.
HDATA<31>
Y0/
G0<M
SB>
HDATA<30>
Y0/
G0<6>
HDATA<29>
Y0/
G0<5>
HDATA<28>
Y0/
G0<4>
HDATA<27>
Y0/
G0<3>
HDATA<26>
Y0/
G0<2>
HDATA<25>
Y0/
G0<1>
HDATA<24>
Y0/
G0<0>
HDATA<23>
Cb0/
G1<
MSB>
HDATA<22>
Cb0/
G1<
6>
HDATA<21>
Cb0/
G1<
5>
HDATA<20>
Cb0/
G1<
4>
HDATA<19>
Cb0/
G1<
3>
HDATA<18>
Cb0/
G1<
2>
HDATA<17>
Cb0/
G1<
1>
HDATA<16>
Cb0/
G1<
0>
HDATA<15>
Y1/
G2<M
SB>
HDATA<14>
Y1/
G2<6>
HDATA<13>
Y1/
G2<5>
HDATA<12>
Y1/
G2<4>
HDATA<11>
Y1/
G2<3>
HDATA<10>
Y1/
G2<2>
HDATA<9>
Y1/
G2<1>
HDATA<8>
Y1/
G2<0>
HDATA<7>
Cr0/G
3<MS
B>
HDATA<6>
Cr0/G
3<6>
HDATA<5>
Cr0/G
3<5>
HDATA<4>
Cr0/G
3<4>
HDATA<3>
Cr0/G
3<3>
HDATA<2>
Cr0/G
3<2>
HDATA<1>
Cr0/G
3<1>
HDATA<0>
Cr0/G
3<0>
CS
DATA<31:
0>
CS
RD
RD
WR
WE
ACK
ACK
IRQ
I
RQ
DREQ
DRE
Q0
DACK
DACK0
MCL
K
74.25M
Hz
DREQ
DRE
Q1
DACK
DACK1
ADV212
32-BI
T HO
ST
COMPRESSED
DATA P
ATH
RAW PIXEL
DATA P
ATH
06389-007
Figure
38
. Host Interface
—
Pixel Interf
ace Mode
ADV212
Rev.
B
| Page
40
of
44
JDATA INTERFAC
E
Fig
ure
39
shows a typical config
uration using JD
A
T
A
with a dedic
at
ed JDA
T
A outp
ut, 1
6
-
bit host, and 10
-
bit CCIR 656.
16-BI
T
HOS
T CPU
FPGA
ADV212
HDATA[
15:0]
DATA[
15:0]
AD
V7189
IRQ
IRQ
ADDR[3:0]
ADDR[3:0]
P[19:
10]
VDATA[11:
2]
FIELD
FIELD
VS
VSYNC
HS
LLC1
HSYNC
MCL
K
27MHz
OSC
VCL
K
VID
EO IN
YCrCb
CS
CS
JDATA[
7:0]
HOLD
VA
LID
RD
RD
WE
WE
ACK
ACK
06389-008
Figure
39
. JDAT
A Applicat
ion
ADV212
Rev.
B
| Page
41
of
44
OUTLINE DIMENSION
S
*COM
PLI
ANT W
I
TH JEDE
C S
T
ANDARDS MO
-192-ABD-
1 WI
TH
EXCE
PTI
ON T
O
PACKAGE
HEIG
HT
AND THI
CKNESS.
DETAI
L A
0.70
0.60
0.50
BALL
DIAM
ETE
R
0.20
COP
LANARI
TY
1.00
BSC
10.00
BSC SQ
A
B
C
D
E
F
G
H
J
K
L
10
8
7
6
3
2
1
9
5
4
11
*
1.31
1.21
1.11
A1 CORNE
R
INDE
X AREA
TOP VI
EW
BALL
A1
CORNE
R
DE
TAIL A
BOTTOM
VIEW
0.50 NO
M
0.30 M
IN
*
1.85
1.71
1.40
12.20
12.00 S
Q
11.80
082406-A
SEAT
ING
PL
ANE
Figure
40
. 121
-
B
all Chip Sca
le Packag
e Ball Grid A
rray [CSP_
BGA]
(BC-
121
-
1)
Dimensions
shown in
millimete
rs
SEAT
ING
PL
ANE
DETAI
L A
0.70
0.60
0.50
BALL
DIAM
ETE
R
COP
LANARI
TY
0.20 M
AX
1.00 BS
C
11.00
BCS SQ
A
B
C
D
E
F
G
J
H
K
L
M
12
11
10
8
7
6
3
2
1
9
5
4
0.53
0.43
A1 CORNE
R
INDE
X AREA
TOP VI
EW
13 .00
BSC SQ
BALL
A1
INDI
CATO
R
DE
TAIL A
BOTTOM
VIEW
*
1.85
MAX
*
1.32
1.21
1.11
*
COM
PLI
ANT W
I
TH JEDE
C STANDARDS
MO
-192-AAD-1 W
IT
H
EXCE
PTI
ON T
O
PACKAGE
HEIG
HT
AND THI
CKNESS.
021506-
A
Figure
41
. 144
-
B
all Chip Sca
le Packag
e Ball Grid A
rray [CSP_
BGA]
(BC-
144
-
3)
Dimensions
shown in
millimete
rs
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
ADV212BBCZ-150
Mfr. #:
Buy ADV212BBCZ-150
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 CODEC w/Integrated Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL
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EMS
Payment:
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