AMIS−30422
http://onsemi.com
24
Programmable Peak−Current
The amplitude of the current waveform in the motor coils
(I
max
) can be programmed through SPI bits <CUR[2:0]>.
The coil current can be calculated as next:
I
max
+ <CUR[2:0]> ń R
SENSE
R
SENSE
is resistor R
1
and R
2
as given in Figure 9,
<CUR[2:0]> is dependant on the REF−pin voltage. This
makes it possible to set the coil current by means of SPI
commands or by adjusting the REF−pin voltage. See also
page 35.
A change in the coil current (<CUR[2:0]>) will be
updated at the next PWM cycle.
Hold Current Setting
A second coil current value can be programmed which is
called the Hold Current (<HOLD_CUR[2:0]>). By enabling
this functionality (<EN_HOLD> = 1), AMIS−30422 will
automatically change the coil current to the programmed
Hold Current value when no NXT pulse is detected for a
time longer than the specified <HOLD_TIME[1:0]>. From
the moment a NXT pulse is detected, AMIS−30422 will
automatically set the coil current back to <CUR[2:0]>. This
functionality makes it easy to add Run and Hold Current
capability to your application.
The HOLDCUR−pin can be used if one wants to select
Run or Hold Current manually. To use this pin,
<EN_HOLD> must be set to 0 (zero). When pulling the
HOLDCUR−pin high, the coil current will be defined by the
<HOLD_CUR[2:0]> value. When pulled low, the coil
current will be defined by the <CUR[2:0]> value. When
<EN_HOLD> is set to 0 (zero) <HOLD_TIME[1:0]> will
have no meaning. Switching between the two coil current
values can be done at any time (= independent of the NXT
frequency). By this the HOLDCUR−pin can also be used to
switch between two coil current values in an easy way (even
when the motor is rotating).
The Hold Current (<HOLD_CUR[2:0]>) is calculated in
the same way as the Run Current (<CUR[2:0]>).
Clear
Logic 0 on the CLR−pin allows normal operation of the
chip. To clear the complete digital inside AMIS−30422, the
CLR−pin needs to be pulled to logic 1 for a minimum time
of t
CLR
(Table 5). Clearing the motor driver can not be done
during Sleep Mode. During a clear the charge pump remains
active. The voltage regulator remains functional during and
after the clear action and the WDb−pin is not activated.
After a clear, NXT pulses can be applied after t
CLR_SET
(see Figure 7).
Speed and Load Angle Output
The SLA−pin provides an output voltage that indicates the
level of the BEMF (Back Electro Magnetic Force) voltage
of the motor. This BEMF voltage is sampled during every
so−called ”coil current zero crossing”. Per coil, two
zero−current positions exist per electrical period, yielding in
a total of four zero−current observation points per electrical
period.
Because of the relatively high recirculation currents in the
coil during current decay, the coil voltage V
COIL
shows a
transient behavior. This transient behavior (which is not the
BEMF) can be made visible or invisible on the SLA−pin by
means of SPI bit <SLAT>. When set to transparent
(<SLAT> = ‘1’), the coil voltage is sampled every PWM
cycle and updated on the SLA−pin (see Figure 18). When set
to not−transparent (<SLAT> = ‘0’), only the last sample
(taken right before leaving the “coil current zero crossing”)
will be copied to the SLA−pin (see Figure 19).
When working in not−transparent mode (<SLAT> = ‘0’)
keep in mind that there is a delay between applying the NXT
pulse (to leave the “coil current zero crossing”) and the
updated voltage on the SLA−pin (see t
SLA_DELAY
in
Figure 19 and Table 5).
