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AMIS30422DBGEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
AMIS−30422
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34
Table 8. SPI REGISTER OVERVIEW
SPI Register AbbreviationAccessAddress
Status Register 4 0x09 R SR4
Predriver Register 0 0x0A R/W PDRV0
Predriver Register 1 0x0B R/W PDRV1
Predriver Register 2 0x0C R/W PDRV2
Predriver Register 3 0x0D R/W PDRV3
Where: R/W = read and write access, R = read access only
Watchdog Register (WR)
The Watchdog Register is located at address 0x00 and can be used to enable the watchdog and set the watchdog time−out.
It can also be used to set the short circuit and open coil detection time−out.
Table 9. WATCHDOG REGISTER
Watchdog Register (WR)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 1 0 0
Data WDEN WDT[3:0] OPEN_COIL[1:0] −
Table 10. WATCHDOG REGISTER PARAMETERS
Parameter Value Value Description Info
WDEN
0 Disable
Enables the watchdog p28
1 Enable
WDT[3:0]
0000 32 ms
Defines the watchdog time−out period. The watchdog needs
to be re−enabled (WDEN) within this time or WDb−pin is ac-
tivated for t
POR
.
p28
0001 64 ms
0010 96 ms
0011 128 ms
0100 160 ms
0101 192 ms
0110 224 ms
0111 256 ms
1000 288 ms
1001 320 ms
1010 352 ms
1011 384 ms
1100 416 ms
1101 448 ms
1110 480 ms
1111 512 ms
OPEN_COIL[1:0]
00 2.56 ms
Defines the open coil detection time−out. If an open coil is
detected for a time longer than OpenTimeOut[1:0], an open
coil (OPEN_X and/or OPEN_Y) will be reported.
Note: Short circuit could trigger open coil detection.
p27
01 0.32 ms
10 20.48 ms
11 163.84 ms
Remark: Bit 0 of Watchdog Register should always be ‘0’ (zero)!
AMIS−30422
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35
Control Register 0 (CR0)
Control Register 0 is located at address 0x01 and is used to set the maximum coil current and stepping mode.
Table 11. CONTROL REGISTER 0
Control Register 0 (CR0)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x01
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 1 1 1
Data SM[3:0] − CUR[2:0]
Table 12. CONTROL REGISTER 0 PARAMETERS
Parameter Value Value Description Info
SM[3:0]
0000 128
th
Defines the 8 stepping modes for the PWM regulator. p23
0001 64
th
0010 32
nd
0011 16
th
0100 8
th
0101 4
th
0110 Half step
0111 Full Step
1111 Full Step + 1/2 rotation
Other Reserved
CUR[2:0]
000 V
REF
/ 40
Defines the maximum voltage over the coil current sense
resistor which defines the maximum coil current.
The maximum coil current is calculated as next:
I
coil
= CUR[2:0] / R
sense
V
REF
= voltage on REF−pin (with a maximum of 2 V)
p24
001 V
REF
/ 20
010 3 x V
REF
/ 40
011 V
REF
/ 10
100 V
REF
/ 8
101 3 x V
REF
/ 20
110 7 x V
REF
/ 40
111 V
REF
/ 5
Control Register 1 (CR1)
Control Register 1 is located at address 0x02 and can used to set the direction, NXT−pin polarity, output configuration of
WDb− and ERRb− pin and to enable PWM jitter. It can also be used to set the coil current zero−crossing.
Table 13. CONTROL REGISTER 1
Control Register 1 (CR1)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x02
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 1 1 0 0 0
Data DIRCTRL NXTP − WDb_OD ERRb_OD PWMJ MINSLATIME[1:0]
AMIS−30422
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36
Table 14. CONTROL REGISTER 1 PARAMETERS
Parameter Value Value Description Info
DIRCTRL
0 CW
Defines the direction of rotation.
Remark:
CW and CCW is relative. Direction of rotation will
be defined by the status of the DIR−pin and connection of
the stepper motor!
p23
1 CCW
NXTP
0 Positive Edge
Defines the active edge on the NXT−pin. p23
1 Negative Edge
WDb_OD
0 Push Pull
Defines the output type of WDb−pin p28
1 Open Drain
ERRb_OD
0 Push Pull
Defines the output type of ERRb−pin p28
1 Open Drain
PWMJ
0 Disabled
Enables or disables PWM jitter p14
1 Enabled
MINSLATIME[1:0]
00
40 ms
Defines the time coil current zero−crossing extension time. p21
01
120 ms
10
200 ms
11
360 ms
Remark: Bit 5 of Control Register 1 should always be ‘0’ (zero)!
Control Register 2 (CR2)
Control Register 2 is located at address 0x03 and can be used to enable the motor driver and to put the motor driver in sleep
mode. It also has some parameters that can be used to set the SLA.
Table 15. CONTROL REGISTER 2
Control Register 2 (CR2)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x03
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Data MOTEN SLP − SLAT SLAG[2:0] SLA_OFFS
Table 16. CONTROL REGISTER 2 PARAMETERS
Parameter Value Value Description Info
MOTEN
0 Disabled
Enables the PWM regulator.
Remark:
the regulator is automatically disabled if one of the
bits in Status Register 1 or 2 is set.
p23
1 Enabled
SLP
0 Normal Mode
Enables the sleep mode (power down mode) p26
1 Sleep Mode
SLAT
0 Not Transparent
Defines the type of SLA sampling. p24
1 Transparent
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

AMIS30422DBGEVB

Mfr. #:
Buy AMIS30422DBGEVB
Manufacturer:
ON Semiconductor
Description:
DAUGHTER BOARD BIP STEP MOTOR
Lifecycle:
New from this manufacturer.
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