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AMIS30422DBGEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
AMIS−30422
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43
Predriver Register 3 (PDRV3)
Predriver Register 3 is located at address 0x0D and can be used to set t
1
(see Figure 11).
Table 35. PREDRIVER REGISTER 3
Predriver Register 3 (PDRV3)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0D
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 1 0 0 0 1
Data - TOP_t1[2:0] - BOT_t1[2:0]
Table 36. PREDRIVER REGISTER 3 PARAMETERS
Parameter Value Value Description Info
TOP_t1[2:0]
000 375 ns
Defines the switch on duration t
1
for the external top MOSFET’s. p13
001 500 ns
010 625 ns
011 750 ns
100 825 ns
101 1000 ns
110 1125 ns
111 1250 ns
BOT_t1[2 :0]
000 375 ns
Defines the switch on duration t
1
for the external bottom MOSFET’s. p13
001 500 ns
010 625 ns
011 750 ns
100 825 ns
101 1000 ns
110 1125 ns
111 1250 ns
AMIS−30422
http://onsemi.com
44
PACKAGE THERMAL CHARACTERISTICS
The AMIS−30422 is available in a NQFP48 package. For
cooling optimizations, the NQFP has an exposed thermal
pad which has to be soldered to the PCB ground plane. The
ground plane needs thermal vias to conduct the heat to the
bottom layer.
Figure 34 gives an example of good heat transfer. The
exposed thermal pad is soldered directly on the top ground
layer (left picture of Figure 34). It’s advised to make the top
ground layer as large as possible (see arrows Figure 34). To
improve the heat transfer even more, the exposed thermal
pad is connected to a bottom ground layer by using thermal
vias (see right picture of Figure 34). It’s advised to make this
bottom ground layer as large as possible and with as less as
possible interruptions.
For precise thermal cooling calculations the major
thermal resistances of the device are given (Table 4). The
thermal media to which the power of the devices has to be
given are:
• Static environmental air (via the case)
• PCB board copper area (via the exposed pad)
The major thermal resistances of the device are the Rth
from the junction to the ambient (Rth
ja
) and the overall Rth
from the junction to exposed pad (Rth
jp
). In Table 4 one can
find the values for the Rth
ja
and Rth
jp
, simulated according
to JESD−51.
The Rth
ja
for 2S2P is simulated conform JEDEC
JESD−51 as follows:
• A 4−layer printed circuit board with inner power planes
and outer (top and bottom) signal layers is used
• Board thickness is 1,46mm (FR4 PCB material)
• The 2 signal layers: 70 um thick copper with an area of
5500 mm
2
copper and 20% conductivity
• The 2 power internal planes: 36 mm thick copper with
an area of 5500 mm
2
copper and 90% conductivity
The Rth
ja
for 1S0P is simulated conform to JEDEC
JESD−51 as follows:
• A 1−layer printed circuit board with only 1 layer
• Board thickness is 1.46 mm (FR4 PCB material)
• The layer has a thickness of 70 mm copper with an area
of 5500 mm
2
copper and 20% conductivity
Figure 34. PCB Ground Plane Layout Condition (left picture displays the top ground layer, right picture displays
the bottom ground layer)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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24
36
35
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32
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30
29
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25
48
47
46
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42
41
40
39
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37
ORDERING INFORMATION
Part No. Peak Current Temperature Range Package Shipping
†
AMIS30422C422G
NA
−40°C to +170°C
NQFP−48 (7 x 7 mm)
(Pb−Free)
Units / Tube
AMIS30422C422MNTWG Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
AMIS−30422
http://onsemi.com
45
PACKAGE DIMENSIONS
NOTE 3
SEATING
PLANE
K
0.15 C
(A3)
A
A1
D2
b
1
13
25
48 37
2X
2X
E2
48X
12
36
L
48X
BOTTOM VIEW
TOP VIEW
SIDE VIEW
QFN48 7x7, 0.5P
CASE 485AJ
ISSUE O
0.15 C
D A B
E
PIN 1
LOCATION
0.08 C
0.05 C
e
0.10
C
0.05
C
A B
C
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO THE PLATED
TERMINAL AND IS MEASURED ABETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM MIN MAX
MILLIMETERS
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.20 0.30
D 7.00 BSC
D2 5.00 5.20
E 7.00 BSC
E2 5.00 5.20
e 0.50 BSC
K 0.20 −−−
L 0.30 0.50
NOTE 4
DIMENSIONS: MILLIMETERS
0.50 PITCH
5.20
0.30
48X
7.30
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1
L
DETAIL A
OPTIONAL CONSTRUCTION
2X SCALE
DETAIL A
e/2
2X
2X
0.63
48X
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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
AMIS−30422/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
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AMIS30422DBGEVB

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DAUGHTER BOARD BIP STEP MOTOR
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