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7
Table 4. DC PARAMETERS
The DC parameters are given for V
BB
and temperature in their operating ranges unless otherwise specified.
Convention: currents flowing in the circuit are defined as positive.
Symbol UnitMaxTypMinRemark/Test ConditionsParameterPin(s)
PREDRIVER
V
SENS
RSENSxx
PWM comparator toggle level Selectable through SPI 1/40 1/5 V
REF
V
SENS_Tol
PWM comparator toggle level
tolerance
22 +22
%
REF INPUT
V
REF
REF
REF input voltage 0 VDD V
V
REF_Range
REF input voltage range 0.25 2 V
V
REF_TOL
Tolerance on maximum VREF_Range 10 +10 %
I
REF_LEAK
REF input leakage V
REF
1.8 V 1 1
mA
R
REF
REF input impedance See also Figure 3 10 20 30
kW
DIGITAL INPUTS
V
IL
CLK, DI,
CSb, NXT,
DIR, CLR,
HOLDCUR
Logic Low Threshold 0 0.3 x V
DD
V
V
IH
Logic High Threshold 0.7 x V
DD
V
DD
V
R
pd
Internal Pull Down Resistor
Csb and CLR excluded,
See also Figure 3
250 1100
kW
R
pu
CSb Internal Pull Up Resistor See also Figure 3 250 1100
kW
DIGITAL OUTPUTS
V
OL
DO,
ERRb,
WDb
Logic low output level
Output set to type 4 (see
Figure 3)
0.5
V
V
OH
Logic high output level V
DD
0.5
V
OL_OPEN
Logic Low level open drain
I
OL
= 8 mA, Output set to type 2
(see Figure 3), DO excluded
0.5
SPEED AND LOAD ANGLE OUTPUT
V
out
SLA
Output Voltage Range 0.5 V
DD
0.5 V
V
off
Output Offset SLApin Selectable through SPI 0.6 1.2 V
V
off_tol
Tolerance on SLA output offset 17 +17 %
G
SLA
Gain of SLApin = V
BEMF
/ V
SLA
Selectable through SPI 0.0625 1
G
SLA_tol
Tolerance on SLA gain 10 +10 %
R
out
Output Resistance SLApin See also Figure 3 1
kW
I
SLA_load
Load current SLApin 0 40
mA
THERMAL WARNING & SHUTDOWN
T
1
Trigger level thermal range 1 See Figure 21 5 15 35 °C
T
2
Trigger level thermal range 2 See Figure 21 55 70 85 °C
T
3
Trigger level thermal range 3 See Figure 21 138 150 162 °C
T
TW
Thermal Warning See Figure 21 138 150 162 °C
T
TSD
Thermal shutdown See Figure 21 T
TW
+ 20 °C
CHARGE PUMP
V
CP
V
BB
VCP
Chargepump overdrive voltage Based on Figure 9 3.5 V
BB
– 2.5 15.75 V
V
CPP
V
CPN
Chargepump pumping voltage 3.5 V
BB
– 2.5 15.75 V
C
pump
External pump capacitor See also C
2
Figure 9 220 nF
C
buffer
CPP CPN External buffer capacitor See also C
3
Figure 9 220 nF
AMIS30422
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8
Table 4. DC PARAMETERS
The DC parameters are given for V
BB
and temperature in their operating ranges unless otherwise specified.
Convention: currents flowing in the circuit are defined as positive.
Symbol UnitMaxTypMinRemark/Test ConditionsParameterPin(s)
PACKAGE THERMAL RESISTANCE VALUE
Rth
ja
Thermal Resistance
JunctiontoAmbient
Simulated Conform
JEDEC JESD51, (2S2P)
30 K/W
Simulated Conform
JEDEC JESD51, (1S0P)
60 K/W
Rth
jp
Thermal Resistance
JunctiontoExposed Pad
0.95 K/W
Table 5. AC PARAMETER The AC parameters are given for V
BB
and temperature in their operating ranges unless otherwise
specified.
Symbol
Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit
INTERNAL OSCILLATOR
f
osc
Frequency of internal oscillator 6.4 8 9.6 MHz
POWERUP
t
PU
POR
Powerup time C
VDD
= 200 nF, See Figure 4 60
ms
t
POR
Reset duration See Figure 4 80 100 120 ms
t
RF
Reset filter time See Figure 4 1 15
ms
t
DSPI
SPI Delay See Figure 4 500
ms
PREDRIVER
f
PWM
PWM frequency
Frequency depends only on
internal oscillator
20 25 30 kHz
t
1
Bridge MOSFET switch on time t
1
Selectable through SPI.
See Figure 11.
375 1250 ns
t
2
Bridge MOSFET switch on time t
2
Selectable through SPI.
See Figure 11.
1250 4750 ns
t
off
Bridge MOSFET switch off time
Selectable through SPI.
See Figure 11.
1250 4750 ns
t
switch_tol
Bridge MOSFET switch on/off toler-
ance
20 +20 %
t
open
Open circuit time out Selectable through SPI 0.32 163.84 ms
topen_acc Open circuit time out accuracy 20 +20 %
t
nocross
Non overlap time Selectable through SPI 0 500 ns
t
nocross_acc
Non overlap accuracy 20 +20 %
AMIS30422
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9
Table 5. AC PARAMETER The AC parameters are given for V
BB
and temperature in their operating ranges unless otherwise
specified.
Symbol UnitMaxTypMinRemark/Test ConditionsParameterPin(s)
DIGITAL INPUTS
t
NXT_HI
NXT Minimum, high pulse width
See Figure 6
625 ns
t
NXT_LO
NXT Minimum, low pulse width 625 ns
t
DIR_SET
NXT set up time, following change of
DIR or <DIRCTRL>
1.28
ms
t
DIR_HOLD
NXT hold time, before change of DIR
or <DIRCTRL>
1.28
ms
t
SLP_SET
<SLP> set up time 300
ms
t
SLP_HOLD
<SLP> hold time 1
ms
t
MOTEN_SET
<MOTEN> set up time 1
ms
t
MOTEN_HO
LD
<MOTEN> hold time 1.28
ms
t
MSP
<MSP[7:0]> update delay 1.28
ms
CLEAR FUNCTION
t
CLR_SET
CLR
Clear set up time See Figure 7 40
ms
t
CLR
Clear duration time See Figure 7 20 90
ms
DIGITAL OUTPUTS
t
H2L
DO, WDb,
ERRb
Output falltime from V
OH
to V
OL
Output type 2, capacitive load
400 pF and pullup resistor of
1.5 kW
50 ns
WATCHDOG
t
WDPR
Prohibited watchdog acknowledge
time
2.5 ms
t
WDTO
Watchdog time out interval 32 512 ms
t
WDTO_acc
Watchdog time out accuracy 20 +20 %
t
WDRD
Watchdog Reset Delay 500 ns
SERIAL PERIPHERAL INTERFACE (SPI)
t
CLK
CLK
SPI Clock period
See Figure 8
1
ms
t
CLK_HIGH
SPI Clock high time 100 ns
t
CLK_LOW
SPI Clock low time 100 ns
t
DI_SET
DI
SPI Data Input set up time 50 ns
t
DI_HOLD
SPI Data Input hold time 50 ns
t
CS_HIGH
CSb
SPI Chip Select high time 2.5
ms
t
CS_SET
SPI Chip Select set up time 100 ns
t
CS_HOLD
SPI Chip Select hold time 100 ns
SPEED AND LOAD ANGLE OUTPUT
t
SLA_DELAY
SLA SLA output update delay
Nottransparent Mode
See Figure 19
60
ms
t
MinSLA
Minimum zero crossing time Selectable through SPI 40 360
ms
t
MinSLA_Acc
Minimum zero crossing accuracy 20 +20 %
CHARGE PUMP
f
CP
CPN CPP Charge pump frequency 160 200 240 kHz
t
CPU
MOTxx Startup time of charge pump
Spec external components in
Table 4
250
ms

AMIS30422DBGEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
DAUGHTER BOARD BIP STEP MOTOR
Lifecycle:
New from this manufacturer.
Delivery:
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