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LTC4417HUF#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
LTC4417
13
4417f
applicaTions inForMaTion
Reduction of the valid operating range can be used to
prevent disconnected high impedance input supplies
from reconnecting. For example, if 3 series connected AA
Alkaline batteries with a total series resistance of 675mΩ
is used to source 500mA, the voltage drop due to the se-
ries resistance would be 337.5mV. Once the batteries are
discharged and are disconnected due to a UV fault, the AA
battery stack would recover the 337.5mV drop across the
internal series resistance. Using the 30mV fixed internal
hysteresis allows only 81mV of hysteresis at the input
pin, possibly allowing the input supply to revalidate and
reconnect. Using external hysteresis, the hysteresis volt-
age can be increased to 400mV, reducing or eliminating
the reconnection issue, as shown in Figure 4.
FILTERING NOISE ON OV AND UV PINS
The LTC4417 provides an 8µs OV/UV fault filter time. If
the 8µs filter time is not sufficient, add a filter capacitor
between the OV or UV pin and GND to extend the fault
filter time and ride through transient events. A UV pin fault
filter time extension capacitor, C
UVF
, is shown in Figure 5.
Use Equation (6) to select C
UVF
for the UV pin and Equa-
tion (7) to select C
OVF
for the OV pin.
C
UVF
= t
DELAY
•
R1+R2+R3
R3 • (R1+R2)
• ln
V
i
– V
f
1V – V
f
⎡
⎣
⎢
⎤
⎦
⎥
(6)
C
OVF
= t
DELAY
•
R1+R2+R3
R1•(R2+R3)
• ln
V
i
– V
f
1V – V
f
⎡
⎣
⎢
⎤
⎦
⎥
(7)
where the final input voltage V
f
and the initial voltage V
i
are the resistively divided down values of the input supply
step, as shown in Figure 6.
Connecting HYS to GND, as shown in Figure 5, selects
an internal 30mV fixed hysteresis, resulting in 3% of the
input supply voltage.
Figure 6. Fault Filter Time Extension
4417 F05
WITHOUT FAULT FILTER
TIME EXTENSION
1V V
OVUV(THR)
V
IN(INIT)
V
IN(FINAL)
t
DELAY
WITH FAULT FILTER
TIME EXTENSION
INPUT SUPPLY STEP
V
i
=
V
IN(INIT)
•(R1+ R2)
R1+R2+ R3
V
f
=
V
IN(FINAL)
•(R1+ R2)
R1+ R2+ R3
Figure 4. Setting a Higher UV Hysteresis to Prevent
Unwanted Reconnections
V1
400mV HYSTERESIS
FULLY CHARGED 3 × AA BATTERY
VALID UV
RANGE
FOR 81mV
HYSTERESIS
VALID UV
RANGE
FOR 400mV
HYSTERESIS
V1 UV FAULT AND
DISCONNECTS
337.5mV RECOVERY
WHEN LOAD IS
DISCONNECTED
81mV HYSTERESIS
2.7V UV THRESHOLD
4417 F06
C
UVF
UV1
V1 INPUT
SUPPLY
LTC4417
V1
1V
1.03V
VALID1
HYS
4417 F04
UV1
VALID
OV1
OV
UV
R1
R2M2
R3
GND
OPTIONAL
FILTER
CAPACITOR
OPTIONAL
DISCONNECT
+
–
OV1
VALID
M1
R
P
V
OUT
+
–
256ms
TIMER
1V
0.97V
Figure 5. LTC4417 Internal Hysteresis with Optional Filter
Capacitor and Manual Disconnect MOSFET
Extending the filter time delay will result in a slower
response to fast UV and OV faults. Extending the UV pin
fault filter time delay will also add delay to the OV pin. If
this is not desirable, separate the single resistive string
into two resistive strings, as shown in Figure 3.
PRIORITY REASSIGNMENT
A connected input supply can be manually disconnected
by artificially creating a UV fault. An example is shown in
Figure 5. When N-channel MOSFET, M2, is turned on, the
LTC4417
14
4417f
applicaTions inForMaTion
UV1 pin is pulled below 1V. The LTC4417 then discon-
nects V1 and connects the next highest valid priority to
V
OUT
. When selecting the external N-channel MOSFET,
be sure to account for drain leakage current when setting
UV and OV thresholds by adjusting the resistive divider to
consume more current.
SELECTING EXTERNAL P-CHANNEL MOSFETS
The LTC4417 drives external back-to-back P-channel
MOSFETs to conduct or block load current between an
input supply and load. When selecting external P-channel
MOSFETs, the key parameters to consider are on-resistance
(R
DS(ON)
), absolute maximum rated drain to source break-
down voltage (BV
DSS(MAX)
), threshold voltage (V
GS(TH)
),
power dissipation, and safe operating area (SOA).
To determine the required R
DS(ON)
use Equation (8), where
V
DROP
is the maximum desired voltage drop across the
two series MOSFETs at full load current, I
L(MAX)
, for the
application. External P-channel MOSFET devices may be
paralleled to further decrease resistance and decrease
power dissipation of each paralleled MOSFET.
R
DS(ON)
≤
V
DROP
2 •I
L(MAX)
(8)
The clamped gate drive output is 4.5V (minimum) from
the common source connection. Select logic level or lower
threshold external MOSFETs to ensure adequate overdrive.
For applications with input supplies lower than the clamp
voltage, choose external MOSFET with thresholds suf-
ficiently lower than the input supply voltage to guarantee
full enhancement.
It is imperative that external P-channel MOSFET devices
never exceed their BV
DSS(MAX)
rating in the application.
Select devices with BV
DSS(MAX)
ratings higher than seen
in the application. Switching inductive supply inputs with
low value input and/or output capacitances may require
additional precautions; see Transient Supply Protection
section in this data sheet for more information.
In normal operation, the external P-channel MOSFET de-
vices are either fully on, dissipating relatively low power,
or off, dissipating no power. However, during slew-rate
controlled start-up, significant power is dissipated in the
external P-channel MOSFETs. The external P-channel
MOSFETs dissipate the maximum amount of power during
the initial slew-rate limited turn on, where the full input
voltage is applied across the MOSFET while it sources
current. Power dissipation immediately starts to decrease
as the output voltage rises, decreasing the voltage
drop
across the MOSFET
s.
A conservative approach for determining if a particular
device is capable of supporting soft-start, is to ensure its
maximum instantaneous power, at the start of the output
slewing, is within the manufacturer’s SOA curve. First
determine the duration of soft-start using Equation (9)
and find the inrush current into the load capacitor using
Equation (10).
t
STARTUP
=
V
IN
5 V/ ms
[ ]
(9)
I
MAXCAP
= C
L
• 5000[V/s] (10)
Using V
IN
and I
MAXCAP
, the power dissipated by the external
MOSFETs during start-up, P
SS
, is defined by Equation(11).
If the LTC4417 soft-starts with a live I
L
, the extra load cur-
rent needs to be added to I
MAXCAP
, and P
SS
is calculated
by Equation (12).
P
SS
= V
IN
• I
MAXCAP
(11)
P
SS
= V
IN
• (I
MAXCAP
+ I
L
) (12)
Check to ensure P
SS
with a t
STARTUP
single pulse duration
lies within the safe operating area (SOA) of the chosen
MOSFET. Ensure the resistive dividers can sink the drain-
source leakage current at the maximum operating tem-
perature. Refer to manufacturer’s data sheet for maximum
drain to source leakage currents, I
DSS
.
A list of suggested P-channel MOSFETs is shown in
Table1. Use procedures outlined in this section and the
SOA curves in the chosen MOSFET manufacturer’s data
sheet to verify suitability for the application.
LTC4417
15
4417f
applicaTions inForMaTion
Table 1. List of Suggested P-Channel MOSFETs
V1, V2, V3 MOSFET V
TH(MAX)
V
GS(MAX)
V
DS(MAX)
MAX RATED
R
DS(ON)
AT 25°C
≤5V Si4465ADY –1V ±8V –8V 9mΩ at –4.5V
11mΩ at –2.5V
≤10V Si4931DY* –1V ±8V –12V 18mΩ at –4.5V
22mΩ at –2.5V
≤18V FDS8433A –1V ±8V –20V 47mΩ at –4.5V
70mΩ at –2.5V
≤18V IRF7324* –1V ±12V –20V 18mΩ at –4.5V
26mΩ at –2.5V
≤28V Si7135DP –3V ±20V –30V 6.2mΩ at –4.5V
≤28V FDS6675BNZ –3V ±20V –30V 22mΩ at –4.5V
≤28V AO4803A* –2.5V ±20V –30V 46mΩ at –4.5V
≤36V SUD50P04 –2.5V ±20V –40V 30mΩ at –4.5V
≤36V FDD4685 –3V ±20V –40V 35mΩ at –4.5V
≤36V FDS4685 –3V ±20V –40V 35mΩ at –4.5V
≤36V Si4909DY* –2.5V ±20V –40V 34mΩ at –4.5V
≤36V Si7489DP –3V ±20V –100V 47mΩ at –4.5V
*Denotes Dual P-Channel
REVERSE VOLTAGE PROTECTION
The LTC4417 is designed to withstand reverse voltages
applied to V1, V2 and V3 with respect to V
OUT
of up to
–84V. The large reverse voltage rating protects 36V input
supplies and downstream devices connected to V
OUT
against high reverse voltage connections of –42V (absolute
maximum) with margin.
Select back-to-
back P-channel MOSFETS with BV
DSS(MAX)
ratings capable of handling any anticipated reverse voltages
between V
OUT
and V1, V2 or V3. Ensure transient voltage
suppressors (TVS) connected to reverse connection pro-
tected inputs (V1, V2 and V3) are bidirectional and input
capacitors are rated for the negative voltage.
REVERSE CURRENT BLOCKING
When switching channels from higher voltages to lower
voltages, the REV comparator verifies the V
OUT
voltage is
below the connecting channel’s voltage by 120mV before
the new channel is allowed to connect to V
OUT
. This ensures
little to no reverse conduction occurs during switching.
An example is shown in Figure 7. V2 is initially connected
to V
OUT
when a higher priority input supply, V1, is inserted.
The LTC4417 validates V1 and disconnects V2, allowing
V
OUT
to decay from 18V to 11.88V at a slew rate determined
by the load current divided by the load capacitance. Once
V
OUT
falls to 11.88V, the LTC4417 connects V1 to V
OUT
.
SELECTING V
OUT
CAPACITANCE
To ensure there is minimal droop at the output, select a
low ESR capacitor large enough to ride through the dead
time between channel switchover. A low ESR bulk capacitor
will reduce IR drops to
the output voltage while the load
current
is sourced from the capacitor. Use Equation (13)
to calculate the load capacitor value that will ride through
the OV/UV comparator delay, t
pVALID(OFF)
, plus the break-
before-make time, t
G(SWITCHOVER)
.
C
L
I
L(MAX)
• t
G(SWITCHOVER)
+ t
pVALID(OFF)
( )
V
OUT_DROOP(MAX)
(13)
where I
L(MAX)
is the maximum load current drawn and
V
OUT_DROOP(MAX)
is the maximum acceptable amount of
voltage droop at the output.
Equation (13) assumes no inrush current limiting circuitry
is required. If it is required, refer to Figure 8 and use the
following Equation (14) for C
L
.
()
≥
++
C
I•tt0.79 •R •C
V
L
L(MAX)
G(SWITCHOVER)pVALID(O FF)
SS
OUT _DROOP(MAX)
(14)
Figure 7. Reverse Current Blocking
V1 VALIDATES
V2 DISCONNECTS
V1 CONNECTS AT
V
OUT
= 11.88V
4417 F07
256ms
V
OUT
V1 = 12V
V
REV
=
120mV
V
OUT
V2 = 18V
V1 = 12V
dV
OUT
dt
=
I
L
C
L
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LTC4417HUF#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Power Management Specialized - PMIC 2.5V to 36V Prioritized Triple PowerPath Controller
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