LTC4417
7
4417f
pin FuncTions
G1, G2, G3: P-Channel MOSFET Gate Drive Outputs. G1,
G2 and G3 are used to control external back-to-back P-
channel MOSFETs. When driven low, G1, G2 and G3 are
clamped 6V below their corresponding VS1, VS2 and VS3.
Connect G1, G2 and G3 to external P-channel MOSFET
gate pins. See Dual Channel Applications Section for con-
necting unused channels.
GND: Device Ground.
HYS: OV/UV Comparator Hysteresis Input. Connecting HYS
to ground sets a fixed 30mV hysteresis for the OV and UV
comparators. Connecting a resistor, R
HYS
, between HYS
and ground disables the internal 30mV hysteresis and sets
a 63mV/R
HYS
hysteresis current which is sourced from
each OV1, OV2 and OV3 and sunk into each UV1, UV2 and
UV3 pin. Connect to ground when not used.
OV1, OV2, OV3: Overvoltage Comparator Inputs. Rising
voltages above 1V signal an over voltage event, invalidating
the respective input supply channel. Connect OV1, OV2 and
OV3 to an external resistive divider from its respective V1,
V2 and V3 to achieve the desired overvoltage threshold.
The comparator hysteresis can be set to an internally fixed
30mV or set externally via the HYS pin. Connect unused
pins to ground.
SHDN: Shutdown Input. Driving SHDN below 0.8V turns
off all external back-to-back P-channel MOSFET devices,
forces the LTC4417 into a low current state, and resets
the 256ms timers used to validate V1, V2 and V3. Driving
SHDN above 0.8V allows channels to validate and connect.
SHDN is pulled high to the internal V
LDO
voltage with a
2µA current source and can be pulled up externally to a
maximum voltage of 36V. Leave open when not used.
UV1, UV2, UV3: Undervoltage Comparator Inputs. Falling
voltages below 1V signal an undervoltage event, invalidat-
ing the respective input supply channel. Connect UV1, UV2
and UV3 through a resistive divider between the respec-
tive V1, V2 and V3 and ground to achieve the desired
undervoltage threshold. The comparator hysteresis can
be set to an internally fixed 30mV or set externally via the
HYS pin. Connect pins from unused channels to ground.
V1: Highest Priority Input Supply. When V1 is within its user
defined OV/UV window for 256ms, it is connected to V
OUT
via its external back-to-back P-channel MOSFETs. Connect
V1 to ground when channel is not used. See Applications
Information for
bypass capacitor recommendations.
V2: Second Priority Input Supply. When V2 is within its
OV/UV window for 256ms, it is connected to V
OUT
via
its external back-to-back P-channel MOSFETs only if V1
does not meet its OV/UV requirements. Connect to ground
when channel is not used. See Applications Information
for bypass capacitor recommendations.
V3: Third Priority Input Supply. When V3 is within its OV/UV
window for 256ms, it is connected to V
OUT
via its external
back-to-back P-channel MOSFETs only if V1 and V2 do
not meet their OV/UV requirements. Connect to ground
when channel is not used. See Applications Information
for bypass capacitor recommendations.
VALID1, VALID2, VALID3: Valid Channel Indicator Outputs.
VALID1, VALID2 and VALID3 are high voltage open drain
outputs that pull low when the respective V1, V2 and V3 are
within the OV/UV window for at least 256ms and release
when the respective V1, V2 and V3 are outside the OV/
UV window. Connect a resistor between VALID1, VALID2
and VALID3 and a desired supply, up to a maximum of
36V, to provide the pull-up. Leave open when not used.
VS
1, VS2, VS3: External P-Channel MOSFET Common
Sour
ce Connection. VS1, VS2 and VS3 supply the higher
voltage of V1, V2 and V3 or V
OUT
to the gate drivers.
Connect VS1, VS2 and VS3 to the respective common
source connection of the back-to-back P-channel MOS-
FETs. Connect to ground when channel is not used. See
Applications Information section for bypass capacitor
recommendations.
V
OUT
: Output Voltage Supply and Sense. V
OUT
is an output
voltage sense pin used to prevent any input supply from
connecting to the output if the output voltage is not at
least 120mV below the input supply voltage. During nor-
mal operation, V
OUT
powers most of the internal circuitry
when its voltage exceeds 2.4V. Connect V
OUT
to the output.
See Applications Information section for bypass capacitor
recommendations.
LTC4417
8
4417f
FuncTional block DiagraM
+
+
LDO
PRIORITIZER
HIGHEST VALID PRIORITY
VB
LDO
V
OUT
V
OUT
VB
LDO
SHDN
I
SHDN
2µA
SHDN
1V
D2
P1
V3V2V1
LDO
SHDN
V
LDO
V
BEST
V3
V2
V1
P2
P3
P4
P5
2.4V
PRIORITIZED
NONOVERLAP
CONTROL
LOGIC
V
BESTGEN
+
VS1
350mV
120mV
GATE
DRIVER
REV
V
GS
VS1
V
LDO
V
LDO
BANDGAP
UVLO
V1
V2
GND
M3
M2
D1
CAS
V
LDO
V
LDO
I
CAS
20µA
V3
+
EN
HYS
EN
I
EN
2µA
1V
0.24V
0.5V
M4
D3
V
LDO
V
LDO
I
LIM
5µA
V
LDO
CURRENT SENSE/8
+
V
LDO
1V
+
V
LDO
I
HYS/8
UV
1V
M1
V
LDO
OV
V
LDO
HYS
+
OTA
30mV
256ms
TIMER
EXTERNAL
HYS
HYSTERESIS
CH1
VALID
UV1
UV2
UV3
OV1
OV2
OV3
CHANNEL 1
VALID1
VALID2
VALID3
+
+
CHANNEL 2
CHANNEL 3
+
+
VS1
VS2
VS3
DZ1
6.2V
G2
G3
4417 BD
G1
+
LTC4417
9
4417f
TiMing DiagraM
t
VALID
t
pVALID(OFF)
t
pG(EN,OFF)
t
pG(EN,ON)
t
pG(SHDN)
4417 TD
t
G(SWITCHOVER)
G2
G1
UV2
UV1
EN
SHDN
VALID2
VALID1

LTC4417HUF#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Power Management Specialized - PMIC 2.5V to 36V Prioritized Triple PowerPath Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union