LTC4417
16
4417f
applicaTions inForMaTion
where R
S
and C
S
are component values shown in Figure8.
The selection of R
S
and C
L
involves an iterative process.
Begin by assuming 0.79 • R
S
• C
S
= 10µs and choosing
C
L
using Equation (14). See the Inrush Current and Input
Voltage Droop section for more details regarding inrush
current limiting circuitry, and for selecting R
S
.
Figure 8. Slew Rate Limiting Gate Drive
C
IN1
68µF
C
S
VS1
LTC4417
G1
V
OUT
V
OUT
4417 F08
R
S
D
S
BAT54
12V WALL
ADAPTER
V1
IRF7324
M1 M2
+
C
L
47µF
+
C
VS1
channel disconnects or 32ms has elapsed. Once soft-start
has terminated, the gate driver quickly turns on and off
external back-to-back P-channel MOSFETs as needed. A
SHDN low to high transition or V
OUT
drooping below 0.7V
reactivates soft-start.
INRUSH CURRENT AND INPUT VOLTAGE DROOP
When switching control of V
OUT
from a lower voltage supply
to a higher voltage supply, the higher voltage supply may
experience significant voltage droop due to high inrush
current during a fast connection to a lower voltage output
bulk capacitor with low ESR. This high inrush current may
be sufficient to trigger an undesirable UV Fault.
To prevent a UV fault when connecting a higher voltage
input to a lower voltage output, without adding any inrush
current limiting, size the input bypass capacitor large
enough to provide the required inrush current, as shown
by Equation (15).
C
V1
≥ C
L
•
V1– V
OUT(INIT)
V1
DROOP
– 1
⎛
⎝
⎜
⎞
⎠
⎟
(15)
where V
OUT(INIT)
is the initial output voltage when being
powered from a supply voltage less than V1, C
V1
is the
bypass capacitor connected to V1, C
L
is the output capaci-
tor and V1
DROOP
is the maximum allowed voltage droop
on V1. Make sure C
V1
is a low ESR capacitor to minimize
the voltage step across the ESR.
In situations where input and output capacitances can-
not be chosen to set the desired maximum input voltage
droop, or the peak inrush current violates the maximum
Pulsed Drain Current (I
DM
) of the external P-channel MOS-
FETs, inrush current can be limited by slew rate limiting
the output voltage. The gate driver can be configured to
slew rate limit the output with a resistor, capacitor and
Schottky diode, as shown in Figure 8. The series resistor
R
S
and capacitor, C
S
, slew rate limit the output, while the
Schottky diode, D
S
, provides a fast turn off path when G1
is pulled to VS1.
With a desired input voltage drop, V1
DROOP
, and known
supply resistance R
SRC
, the series resistance, R
S
, can
be calculated with Equation (16), where ∆V
G(SINK)
is
the LTC4417’s sink clamp voltage, V
GS
is the external
GATE DRIVER
When turning a channel on, the LTC4417 pulls the common
gate connection (G1, G2 and G3) down with a P-channel
source follower and a 2µA current source. VS1, VS2 and
VS3 voltages at or above 5V will produce rising slew rates
of 12V/µs and falling slew rates of 4V/µs with 10nF between
the VS and G pins. VS1, VS2 and VS3 voltages lower than
5V will result in lower slew rates, see typical curves for
more detail. As G1, G2 and G3 approaches the 6.2V clamp
voltage, the source follower smoothly reduces its current
while the 2µA hold current continues to pull G1, G2 and
G3 to the final clamp voltage, back biasing the source
follower. Clamping the G1, G2 and G3 voltage prevents
any overvoltage stress on the gate to source oxide of the
external back-to-back P-channel MOSFETs. If leakage into
G1, G2 and G3 exceeds the 2µA hold current, the G1, G2
and G3 voltage will rise above the clamp voltage, where
the source follower enhances to sink the excess current.
When turning a channel off, the gate driver
pulls the com-
mon
gate to the common source with a switch having an
on-resistance of 16Ω, to effect a quick turn-off.
To minimize inrush current at start-up, the gate driver soft-
starts the gate drive of the first input to connect to V
OUT
.
The gate pin is regulated to create a constant 5V/ms rise
rate on V
OUT
. Slew rate control is terminated when any
