Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
10
Figure 8. I/O Cell
Each output supports a variety of output standards dependent on the V
CCO
supplied to its I/O bank. Outputs can
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the V
CCO
supplied to its I/O bank. The I/O standards supported are:
LVTTL LVCMOS 1.8
LVCMOS 3.3 3.3V PCI Compatible
LVCMOS 2.5
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
configured to be a Pull-up Resistor.
Each LA-ispMACH 4000V/Z automotive device I/O has an individually programmable output slew rate control bit.
Each output can be individually configured for fast slew or slow slew. The typical edge rate difference between fast
and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will intro-
duce fewer reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well ter-
minated lines, the fast slew rate can be used to achieve the highest speed.
Global OE Generation
Most LA-ispMACH 4000V/Z automotive family devices have a 4-bit wide Global OE Bus, except the LA-ispMACH
4032V and LA-ispMACH4032Z devices that have a 2-bit wide Global OE Bus. This bus is derived from a 4-bit inter-
nal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be
inverted.
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
128-macrocell device (with 16 blocks), each line of the bus is driven from 8 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
GOE 0
From ORP
*Global fuses
From ORP
To Macrocell
To GRP
GOE 1
GOE 2
GOE 3
VCC
V
CCO
V
CCO
**
*
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
11
Figure 9. Global OE Generation for All Devices Except LA-ispMACH 4032V/Z
Figure 10. Global OE Generation for LA-ispMACH 4032V/Z
Zero Power/Low Power and Power Management
The LA-ispMACH 4000V/Z automotive family is designed with high speed low power design techniques to offer
both high speed and low power. With an advanced E
2
low power cell and non sense-amplifier design approach (full
CMOS logic approach), the LA-ispMACH 4000V/Z automotive family offers SuperFAST pin-to-pin speeds, while
simultaneously delivering low standby power without needing any “turbo bits” or other power management
schemes associated with a traditional sense-amplifier approach.
Shared PTOE
(Block 0)
Shared PTOE
(Block n)
Global
Fuses
GOE (0:3)
to I/O cells
Internal Global OE
PT Bus
(4 lines)
4-Bit
Global OE Bus
Global OE
Fuse connection
Hard wired
Shared PTOE
(Block 0)
Shared PTOE
(Block 1)
Global
Fuses
GOE (3:0)
to I/O cells
Internal Global OE
PT Bus
(2 lines)
4-Bit
Global OE Bus
Global OE
Fuse connection
Hard wired
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
12
The zero power LA-ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design
changes, the LA-ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.
IEEE 1149.1-Compliant Boundary Scan Testability
All LA-ispMACH 4000V/Z automotive devices have boundary scan cells and are compliant to the IEEE 1149.1
standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan
path that can access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition,
these devices can be linked into a board-level serial scan path for more board-level testing. The test access port
operates with an LVCMOS interface that corresponds to the power supply voltage.
I/O Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The LA-ispMACH 4000V/Z automotive fam-
ily of devices allows this by offering the user the ability to quickly configure the physical nature of the I/O cells. This
quick configuration takes milliseconds to complete, whereas it takes seconds for the entire device to be pro-
grammed. Lattice's ispVM™ System programming software can either perform the quick configuration through the
PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inven-
tory levels, higher quality and the ability to make in-field modifications. The LA-ispMACH 4000V/Z automotive
devices provide In-System Programming (ISP™) capability through the Boundary Scan Test Access Port. This
capability has been implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1
standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, users get the ben-
efit of a standard, well-defined interface. All LA-ispMACH 4000V/Z automotive devices are also compliant with the
IEEE 1532 standard.
The LA-ispMACH 4000V/Z automotive devices can be programmed across the commercial temperature and volt-
age range. The PC-based Lattice software facilitates in-system programming of LA-ispMACH 4000V/Z automotive
devices. The software takes the JEDEC file output produced by the design implementation software, along with
information about the scan chain, and creates a set of vectors used to drive the scan chain. The software can use
these vectors to drive a scan chain via the parallel port of a PC. Alternatively, the software can output files in for-
mats understood by common automated test equipment. This equipment can then be used to program LA-
ispMACH 4000V/Z automotive devices during the testing of a circuit board.
User Electronic Signature
The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the
device, stored in E
2
CMOS memory. The LA-ispMACH 4000V/Z automotive device contains 32 UES bits that can be
configured by the user to store unique data such as ID codes, revision numbers or inventory control codes.
Security Bit
A programmable security bit is provided on the LA-ispMACH 4000V/Z automotive devices as a deterrent to unau-
thorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the pro-
grammed pattern by a device programmer, securing proprietary designs from competitors. Programming and
verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.
Hot Socketing
The LA-ispMACH 4000V/Z automotive devices are well-suited for applications that require hot socketing capability.
Hot socketing a device requires that the device, during power-up and down, can tolerate active signals on the I/Os

LA4032ZC-75TN48E

Mfr. #:
Manufacturer:
Lattice
Description:
CPLD - Complex Programmable Logic Devices Auto Grade (AEC-Q100 ) ispMACH4032Z
Lifecycle:
New from this manufacturer.
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