LA4032ZC-75TN48E Datasheet LA4032ZC-75TN48E, LA4032V-75TN44E, LA4064V-75TN48E | P7-P9

Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet

• Block CLK3

• PT Clock

• PT Clock Inverted

• Shared PT Clock

• Ground

Clock Enable Multiplexer

Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-

lowing four sources:

• PT Initialization/CE

• PT Initialization/CE Inverted

• Shared PT Clock

• Logic High

Initialization Control

The LA-ispMACH 4000V/Z automotive family architecture accommodates both block-level and macrocell-level set

and reset capability. There is one block-level initialization term that is distributed to all macrocell registers in a GLB.

At the macrocell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for

set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be

exchanged, providing ﬂexibility.

Note that the reset/preset swapping selection feature affects power-up reset as well. All ﬂip-ﬂops power up to a

known state for predictable system initialization. If a macrocell is conﬁgured to SET on a signal from the block-level

initialization, then that macrocell will be SET during device power-up. If a macrocell is conﬁgured to RESET on a

signal from the block-level initialization or is not conﬁgured for set/reset, then that macrocell will RESET on power-

up. To guarantee initialization values, the V

rise must be monotonic, and the clock must be inactive until the reset

delay time has elapsed.

GLB Clock Generator

Each LA-ispMACH 4000V/Z automotive device has up to four clock pins that are also routed to the GRP to be used

as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four

clock signals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of com-

binations of the true and complement edges of the global clock signals.

Figure 6. GLB Clock Generator

CLK0

CLK1

CLK2

CLK3

Block CLK0

Block CLK1

Block CLK2

Block CLK3

Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet

Output Routing Pool (ORP)

The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.

This provides greater ﬂexibility in determining the pinout and allows design changes to occur without affecting the

pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This

allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-

put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the

output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the LA-ispMACH 4000V/Z family

consists of the following elements:

• Output Routing Multiplexers

• OE Routing Multiplexers

• Output Routing Pool Bypass Multiplexers

Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each

ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.

Figure 7. ORP Slice

Output Routing Multiplexers

The details of connections between the macrocells and the I/O cells vary across devices and within a device

dependent on the maximum number of I/Os available. Tables 6-10 provide the connection details.

Table 6. ORP Combinations for I/O Blocks with 8 I/Os

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M2, M3, M4, M5, M6, M7, M8, M9

I/O 2 M4, M5, M6, M7, M8, M9, M10, M11

I/O 3 M6, M7, M8, M9, M10, M11, M12, M13

I/O 4 M8, M9, M10, M11, M12, M13, M14, M15

I/O 5 M10, M11, M12, M13, M14, M15, M0, M1

I/O 6 M12, M13, M14, M15, M0, M1, M2, M3

I/O 7 M14, M15, M0, M1, M2, M3, M4, M5

Out

ut Routin

Multi

lexer

OE Routing Multiplexer

ORP

Bypass

Multiplexer

From Macrocell

From PTOE

To I/O

Cell

To I/O

Cell

Output

5-PT Fast Path

Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet

Table 7. ORP Combinations for I/O Blocks with 16 I/Os

Table 8. ORP Combinations for I/O Blocks with 12 I/Os

ORP Bypass and Fast Output Multiplexers

The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the

ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also

allows the register output to bypass the ORP to achieve faster t

Output Enable Routing Multiplexers

The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.

I/O Cell

The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus

maintenance circuitry. Figure 8 details the I/O cell.

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M1, M2, M3, M4, M5, M6, M7, M8

I/O 2 M2, M3, M4, M5, M6, M7, M8, M9

I/O 3 M3, M4, M5, M6, M7, M8, M9, M10

I/O 4 M4, M5, M6, M7, M8, M9, M10, M11

I/O 5 M5, M6, M7, M8, M9, M10, M11, M12

I/O 6 M6, M7, M8, M9, M10, M11, M12, M13

I/O 7 M7, M8, M9, M10, M11, M12, M13, M14

I/O 8 M8, M9, M10, M11, M12, M13, M14, M15

I/O 9 M9, M10, M11, M12, M13, M14, M15, M0

I/O 10 M10, M11, M12, M13, M14, M15, M0, M1

I/O 11 M11, M12, M13, M14, M15, M0, M1, M2

I/O 12 M12, M13, M14, M15, M0, M1, M2, M3

I/O 13 M13, M14, M15, M0, M1, M2, M3, M4

I/O 14 M14, M15, M0, M1, M2, M3, M4, M5

I/O 15 M15, M0, M1, M2, M3, M4, M5, M6

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M1, M2, M3, M4, M5, M6, M7, M8

I/O 2 M2, M3, M4, M5, M6, M7, M8, M9

I/O 3 M4, M5, M6, M7, M8, M9, M10, M11

I/O 4 M5, M6, M7, M8, M9, M10, M11, M12

I/O 5 M6, M7, M8, M9, M10, M11, M12, M13

I/O 6 M8, M9, M10, M11, M12, M13, M14, M15

I/O 7 M9, M10, M11, M12, M13, M14, M15, M0

I/O 8 M10, M11, M12, M13, M14, M15, M0, M1

I/O 9 M12, M13, M14, M15, M0, M1, M2, M3

I/O 10 M13, M14, M15, M0, M1, M2, M3, M4

I/O 11 M14, M15, M0, M1, M2, M3, M4, M5

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

LA4032ZC-75TN48E

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CPLD - Complex Programmable Logic Devices Auto Grade (AEC-Q100 ) ispMACH4032Z

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LA4032ZC-75TN48E

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