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LA4032ZC-75TN48E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
13
and inputs without being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active
signals. The LA-ispMACH 4000V/Z automotive devices provide this capability for input voltages in the range 0V to
3.0V.
Density Migration
The LA-ispMACH 4000V/Z automotive family has been designed to ensure that different density devices in the
same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing
design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utili-
zation design targeted for a high density device to a lower density device. However, the exact details of the final
resource utilization will impact the likely success in each case.
AEC-Q100 Tested and Qualified
The Automotive Electronics Council (AEC) consists of two committees: the Quality Systems Committee and the
Component Technical Committee. These committees are composed of representatives from sustaining and other
associate members. The AEC Component Technical Committee is the standardization body for establishing stan-
dards for reliable, high quality electronic components. In particular, the AEC-Q100 specification “Stress Test for
Qualification for Integrated Circuits” defines qualification and re-qualification requirements for electronic compo-
nents. Components meeting these specifications are suitable for use in the harsh automotive environment without
additional component-level qualification testing. Lattice's LA-ispMACH 4000V/Z and LA-MachXO devices com-
pleted and passed the requirements of the AEC-Q100 specification.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
14
Absolute Maximum Ratings
1, 2, 3
LA-ispMACH 4000V (3.3V) LA-ispMACH 4000Z (1.8V)
Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 2.5V
Output Supply Voltage (V
CCO
) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V
Input or I/O Tristate Voltage Applied
4, 5
. . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature (T
j
) with Power Applied . . . . . . . . . . -55 to 150°C . . . . . . . . . . . . . . . -55 to 150°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.
2. Compliance with Lattice Ther
mal Management document is required.
3. All voltages referenced to GND.
4. Undershoot of -2V and overshoot of (V
IH
(MAX) + 2V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns.
5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
Recommended Operating Conditions
Erase Reprogram Specifications
Hot Socketing Characteristics
1,2,3
Symbol Parameter Min. Max. Units
V
CC
LA-ispMACH 4000V Supply Voltage 3.0 3.6 V
LA-ispMACH 4000Z Supply Voltage 1.7 1.9 V
LA-ispMACH 4000Z, Extended Functional Voltage Operations 1.6
1
1.9 V
T
A
Ambient Temperature (Automotive) -40 125 C
1. Devices operating at 1.6V can expect performance degradation up to 35%.
Parameter Min. Max. Units
Erase/Reprogram Cycle 1,000 — Cycles
Note: Valid over commercial temperature range.
Symbol Parameter Condition Min. Typ. Max. Units
I
DK
Input or I/O Leakage Current
0 ≤ V
IN
≤ 3.0V, Tj = 105°C — ±30 ±150 µA
0 ≤ V
IN
≤ 3.0V, Tj = 130°C — ±30 ±200 µA
1. Insensitive to sequence of V
CC
or V
CCO.
However, assumes monotonic rise/fall rates for V
CC
and V
CCO,
provided (V
IN
- V
CCO
) ≤ 3.6V.
2. 0 < V
CC
< V
CC
(MAX), 0 < V
CCO
< V
CCO
(MAX).
3. I
DK
is additive to I
PU
, I
PD
or I
BH
. Device defaults to pull-up until fuse circuitry is active.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
15
I/O Recommended Operating Conditions
DC Electrical Characteristics
Over Recommended Operating Conditions
Standard
V
CCO
(V)
1
Min. Max.
LVTTL 3.0 3.6
LVCMOS 3.3 3.0 3.6
Extended LVCMOS 3.3
2
2.7 3.6
LVCMOS 2.5 2.3 2.7
LVCMOS 1.8 1.65 1.95
PCI 3.3 3.0 3.6
1. Typical values for V
CCO
are the average of the min. and max. values.
2. LA-ispMACH 4000Z only.
Symbol Parameter Condition Min. Typ. Max. Units
I
IL
, I
IH
1, 4
Input Leakage Current
(LA-ispMACH 4000Z)
0 ≤ V
IN
< V
CCO
— 0.5 1 µA
I
IH
1, 2
Input High Leakage Current
(LA-ispMACH 4000V)
3.6V < V
IN
≤ 5.5V, T
j
= 105°C
3.0V ≤ V
CCO
≤ 3.6V
— — 20 µA
3.6V < V
IN
≤ 5.5V, T
j
= 130°C
3.0V ≤ V
CCO
≤ 3.6V
— — 50 µA
Input High Leakage Current
(LA-ispMACH 4000Z)
V
CCO
< V
IN
≤ 5.5V — — 10 µA
I
PU
I/O Weak Pull-up Resistor Current
(LA-ispMACH 4000V)
0 ≤ V
IN
≤ 0.7V
CCO
-30 — -200 µA
I/O Weak Pull-up Resistor Current
(LA-ispMACH 4000Z)
0 ≤ V
IN
≤ 0.7V
CCO
-30 — -150 µA
I
PD
I/O Weak Pull-down Resistor Current V
IL
(MAX) ≤ V
IN
≤ V
IH
(MIN) 30 — 150 µA
I
BHLS
Bus Hold Low Sustaining Current V
IN
= V
IL
(MAX) 30 — — µA
I
BHHS
Bus Hold High Sustaining Current V
IN
= 0.7 V
CCO
-30 — — µA
I
BHLO
Bus Hold Low Overdrive Current 0V ≤ V
IN
≤ V
BHT
— — 150 µA
I
BHHO
Bus Hold High Overdrive Current V
BHT
≤ V
IN
≤ V
CCO
— — -150 µA
V
BHT
Bus Hold Trip Points — V
CCO
* 0.35 — V
CCO
* 0.65 V
C
1
I/O Capacitance
3
V
CCO
= 3.3V, 2.5V, 1.8V —
8
—
pf
V
CC
= 1.8V, V
IO
= 0 to V
IH
(MAX) — —
C
2
Clock Capacitance
3
V
CCO
= 3.3V, 2.5V, 1.8V —
6
—
pf
V
CC
= 1.8V, V
IO
= 0 to V
IH
(MAX) — —
C
3
Global Input Capacitance
3
V
CCO
= 3.3V, 2.5V, 1.8V —
6
—
pf
V
CC
= 1.8V, V
IO
= 0 to V
IH
(MAX) — —
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V ≤ V
CCO
≤ 3.6V.
3. T
A
= 25°C, f = 1.0MHz.
4. I
IH
excursions of up to 1.5µA maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of
the device’s I/O pins.
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LA4032ZC-75TN48E

Mfr. #:
Buy LA4032ZC-75TN48E
Manufacturer:
Lattice
Description:
CPLD - Complex Programmable Logic Devices Auto Grade (AEC-Q100 ) ispMACH4032Z
Lifecycle:
New from this manufacturer.
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