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LA4032ZC-75TN48E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
19
LA-ispMACH 4000V/Z External Switching Characteristics
Over Recommended Operating Conditions
Parameter Description
1, 2, 3
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
UnitsMin. Max. Min. Max.
t
PD
5-PT bypass combinatorial propagation delay — 7.5 — 7.5 ns
t
PD_MC
20-PT combinatorial propagation delay through macro-
cell
— 8.0 — 8.0 ns
t
S
GLB register setup time before clock 4.5 — 4.5 — ns
t
ST
GLB register setup time before clock with T-type regis-
ter
4.7 — 4.7 — ns
t
SIR
GLB register setup time before clock, input register
path
1.7 — 1.4 — ns
t
SIRZ
GLB register setup time before clock with zero hold 2.7 — 2.7 — ns
t
H
GLB register hold time after clock 0.0 — 0.0 — ns
t
HT
GLB register hold time after clock with T-type register 0.0 — 0.0 — ns
t
HIR
GLB register hold time after clock, input register path 1.0 — 1.3 — ns
t
HIRZ
GLB register hold time after clock, input register path
with zero hold
0.0 — 0.0 — ns
t
CO
GLB register clock-to-output delay — 4.5 — 4.5 ns
t
R
External reset pin to output delay — 9.0 — 9.0 ns
t
RW
External reset pulse duration 4.0 — 4.0 — ns
t
PTOE/DIS
Input to output local product term output enable/dis-
able
— 9.0 — 9.0 ns
t
GPTOE/DIS
Input to output global product term output enable/dis-
able
— 10.3 — 10.5 ns
t
GOE/DIS
Global OE input to output enable/disable — 7.0 — 7.0 ns
t
CW
Global clock width, high or low 2.8 — 2.8 — ns
t
GW
Global gate width low (for low transparent) or high (for
high transparent)
2.8 — 2.8 — ns
t
WIR
Input register clock width, high or low 2.8 — 2.8 — ns
f
MAX
4
Clock frequency with internal feedback — 168 — 168 MHz
f
MAX
(Ext.) Clock frequency with external feedback, [1/ (t
S
+ t
CO
)] — 111 — 111 MHz
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Timing v.3.2
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
20
Timing Model
The task of determining the timing through the LA-ispMACH 4000V/Z automotive family, like any CPLD, is relatively
simple. The timing model provided in Figure 11 shows the specific delay paths. Once the implementation of a given
function is determined either conceptually or from the software report file, the delay path of the function can easily
be determined from the timing model. The Lattice design tools report the timing delays based on the same timing
model for a particular design. Note that the internal timing parameters are given for reference only, and are not
tested. The external timing parameters are tested and guaranteed for every device. For more information on the
timing model and usage, refer to TN1004, ispMACH 4000 Timing Model Design and Usage Guidelines.
Figure 11. LA-ispMACH 4000V/Z Automotive Timing Model
DATA
MC Reg.
C.E.
S/R
Q
SCLK
IN
OE
In/Out
Delays
In/Out
Delays
Control
Delays
Register/Latch
Delays
Routing/GLB Delays
Out
Note: Italicized items are optional delay adders.
t
FBK
Feedback
From
Feedback
t
BUF
t
PDb
t
MCELL
t
PTCLK
t
BCLK
t
PTSR
t
BSR
t
GPTOE
t
PTOE
t
EXP
t
ROUTE
t
BLA
t
INREG
t
INDIO
t
IN
t
IOI
t
GCLK_IN
t
IOI
t
GOE
t
IOI
t
PDi
t
IOO
t
ORP
t
EN
t
DIS
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
21
LA-ispMACH 4000V/Z Internal Timing Parameters
Over Recommended Operating Conditions
Parameter Description
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
UnitsMin. Max. Min. Max.
In/Out Delays
t
IN
Input Buffer Delay — 1.50 — 1.80 ns
t
GOE
Global OE Pin Delay — 6.04 — 4.30 ns
t
GCLK_IN
Global Clock Input Buffer Delay — 2.28 — 2.15 ns
t
BUF
Delay through Output Buffer — 1.50 — 1.30 ns
t
EN
Output Enable Time — 0.96 — 2.70 ns
t
DIS
Output Disable Time — 0.96 — 2.70 ns
Routing/GLB Delays
t
ROUTE
Delay through GRP — 2.26 — 2.50 ns
t
MCELL
Macrocell Delay — 1.45 — 1.00 ns
t
INREG
Input Buffer to Macrocell Register Delay — 0.96 — 1.00 ns
t
FBK
Internal Feedback Delay — 0.00 — 0.05 ns
t
PDb
5-PT Bypass Propagation Delay — 2.24 — 1.90 ns
t
PDi
Macrocell Propagation Delay — 1.24 — 1.00 ns
Register/Latch Delays
t
S
D-Register Setup Time (Global Clock) 1.57 — 1.35 — ns
t
S_PT
D-Register Setup Time (Product Term Clock) 1.32 — 2.45 — ns
t
ST
T-Register Setup Time (Global Clock) 1.77 — 1.55 — ns
t
ST_PT
T-Register Setup Time (Product Term Clock) 1.32 — 2.75 — ns
t
H
D-Register Hold Time 2.93 — 3.15 — ns
t
HT
T-Register Hold Time 2.93 — 3.15 — ns
t
SIR
D-Input Register Setup Time (Global Clock) 1.57 — 0.75 — ns
t
SIR_PT
D-Input Register Setup Time (Product Term
Clock)
1.45 —
1.45 —
ns
t
HIR
D-Input Register Hold Time (Global Clock) 1.18 — 1.95 — ns
t
HIR_PT
D-Input Register Hold Time (Product Term
Clock)
1.18 —
1.18 —
ns
t
COi
Register Clock to Output/Feedback MUX Time — 0.67 — 1.05 ns
t
CES
Clock Enable Setup Time 2.25 — 2.00 — ns
t
CEH
Clock Enable Hold Time 1.88 — 0.00 — ns
t
SL
Latch Setup Time (Global Clock) 1.57 — 1.65 — ns
t
SL_PT
Latch Setup Time (Product Term Clock) 1.32 — 2.15 — ns
t
HL
Latch Hold Time 1.17 — 1.17 — ns
t
GOi
Latch Gate to Output/Feedback MUX Time — 0.33 — 0.33 ns
t
PDLi
Propagation Delay through Transparent Latch to
Output/Feedback MUX
— 0.25
— 0.25
ns
t
SRi
Asynchronous Reset or Set to Output/Feedback
MUX Delay
0.28 —
— 0.28
ns
t
SRR
Asynchronous Reset or Set Recovery Time 1.67 — — 1.67 ns
Control Delays
t
BCLK
GLB PT Clock Delay — 1.12 — 1.25 ns
t
PTCLK
Macrocell PT Clock Delay — 0.87 — 1.25 ns
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LA4032ZC-75TN48E

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Manufacturer:
Lattice
Description:
CPLD - Complex Programmable Logic Devices Auto Grade (AEC-Q100 ) ispMACH4032Z
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