Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
23
LA-ispMACH 4000V/Z Timing Adders
1
Adder Type Base Parameter Description
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
UnitsMin. Max. Min. Max.
Optional Delay Adders
t
INDIO
t
INREG
Input register delay — 1.00 — 1.30 ns
t
EXP
t
MCELL
Product term expander delay — 0.33 — 0.50 ns
t
ORP
— Output routing pool delay — 0.05 — 0.40 ns
t
BLA
t
ROUTE
Additional block loading adder — 0.05 — 0.05 ns
t
IOI
Input Adjusters
LVTTL_in t
IN
, t
GCLK_IN
, t
GOE
Using LVTTL standard — 0.60 — 0.60 ns
LVCMOS33_in t
IN
, t
GCLK_IN
, t
GOE
Using LVCMOS 3.3 standard — 0.60 — 0.60 ns
LVCMOS25_in t
IN
, t
GCLK_IN
, t
GOE
Using LVCMOS 2.5 standard — 0.60 — 0.60 ns
LVCMOS18_in t
IN
, t
GCLK_IN
, t
GOE
Using LVCMOS 1.8 standard — 0.00 — 0.00 ns
PCI_in t
IN
, t
GCLK_IN
, t
GOE
Using PCI compatible input — 0.60 — 0.60 ns
t
IOO
Output Adjusters
LVTTL_out t
BUF
, t
EN
, t
DIS
Output configured as TTL buffer — 0.20 — 0.20 ns
LVCMOS33_out t
BUF
, t
EN
, t
DIS
Output configured as 3.3V buffer — 0.20 — 0.20 ns
LVCMOS25_out t
BUF
, t
EN
, t
DIS
Output configured as 2.5V buffer — 0.10 — 0.10 ns
LVCMOS18_out t
BUF
, t
EN
, t
DIS
Output configured as 1.8V buffer — 0.00 — 0.00 ns
PCI_out t
BUF
, t
EN
, t
DIS
Output configured as PCI
compatible buffer
— 0.20 — 0.20 ns
Slow Slew t
BUF
, t
EN
Output configured for slow slew
rate
— 1.00 — 1.00 ns
Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.3.2
1. Refer to TN1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
