P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 34 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt
generated if enabled. The 16-bit CCU timer may also be used as an 8-bit up/down timer.
7.22.4 Output compare
There are four output compare channels: A, B, C and D. Each output compare channel
needs to be enabled in order to operate and the user will have to set the associated I/O
pin to the desired output mode to connect the pin. When the contents of the timer matches
that of a capture compare control register, the Timer Output Compare Interrupt Flag
(TOCFx) becomes set. An interrupt will occur if enabled.
7.22.5 Input capture
Input capture is always enabled. Each time a capture event occurs on one of the two input
capture pins, the contents of the timer is transferred to the corresponding 16-bit input
capture register. The capture event can be programmed to be either rising or falling edge
triggered. A simple noise filter can be enabled on the input capture by enabling the Input
Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of
the same value in order to recognize an edge as a capture event. An event counter can be
set to delay a capture by a number of capture events.
7.22.6 PWM operation
PWM operation has two main modes, symmetrical and asymmetrical.
In asymmetrical PWM operation the CCU timer operates in down-counting mode
regardless of the direction control bit.
In symmetrical mode, the timer counts up/down alternately. The main difference from
basic timer operation is the operation of the compare module, which in PWM mode is
used for PWM waveform generation.
As with basic timer operation, when the PWM (compare) pins are connected to the
compare logic, their logic state remains unchanged. However, since bit FCO is used to
hold the halt value, only a compare event can change the state of the pin.
Fig 7. Asymmetrical PWM, down-counting
TOR2
compare value
timer value
non-inverted
inverted
0x0000
002aaa893
P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 35 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
7.22.7 Alternating output mode
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
7.22.8 PLL operation
The PWM module features a Phase Locked Loop that can be used to generate a
CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module
provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal
frequency is 1 MHz or higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and
generates an output signal of 32 times the input frequency. This signal is used to clock the
timer. The user will have to set a divider that scales PCLK by a factor from 1 to 16. This
divider is found in the SFR register TCR21. The PLL frequency can be expressed as
shown in Equation 1:
(1)
Where: N is the value of PLLDV3:0.
Fig 8. Symmetrical PWM
TOR2
compare value
timer value
non-inverted
inverted
002aaa894
0
Fig 9. Alternate output mode
TIMER VALUE
002aaa895
0
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
PWM OUTPUT (OCA or OCC)
PWM OUTPUT (OCB or OCD)
PLL frequency
PCLK
N1+()
------------------
=
P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 36 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to
PCLK16.
7.22.9 CCU interrupts
There are seven interrupt sources on the CCU which share a common interrupt vector.
7.23 UART
The P89LPC9351 has an enhanced UART that is compatible with the conventional 80C51
UART except that Timer 2 overflow cannot be used as a baud rate source. The
P89LPC9351 does include an independent baud rate generator. The baud rate can be
selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent
baud rate generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, automatic address recognition,
selectable double buffering and several interrupt options. The UART can be operated in
four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.23.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
1
16
of the CPU clock
frequency.
Fig 10. Capture/compare unit interrupts
002aaa896
interrupt to
CPU
TOIE2 (TICR2.7)
TOIF2 (TIFR2.7)
TICIE2A (TICR2.0)
TICF2A (TIFR2.0)
TICIE2B (TICR2.1)
TICF2B (TIFR2.1)
TOCIE2A (TICR2.3)
TOCF2A (TIFR2.3)
TOCIE2B (TICR2.4)
TOCF2B (TIFR2.4)
TOCIE2C (TICR2.5)
TOCF2C (TIFR2.5)
TOCIE2D (TICR2.6)
TOCF2D (TIFR2.6)
EA (IEN0.7)
ECCU (IEN1.4)
PRIORITY
ENCODER
other
interrupt
sources
ENCINT.0
ENCINT.1
ENCINT.2

P89LPC9351FDH,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU Enhanced LPC935
Lifecycle:
New from this manufacturer.
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